Double-folded cascode operational amplifier

An operational amplifier comprising:

• high and low voltage supply lines,
• an input stage having at least one differential input transistor pair connected to have their currents controlled by a differential input signal, a current source connected to supply a differential current from one of said voltage supply lines to said input transistors, and a pair of input resistors connected between said transistors and the other of said voltage supply lines,
• a cascode gain stage having at least one pair of cascode gain transistors providing a gain stage voltage output and connected to said input transistor pairs so that a change in the differential input signal produces a corresponding change via said input resistors in said gain stage voltage output,
• an output node, and
• an output stage interconnecting said output node with said gain stage output, said output stage including transistor-resistor circuitry producing an output current at said output node that varies in response to changes in the gain stage voltage output, said transistor-resistor circuitry including a pair of output bipolar transistors of opposite conductivities that have their emitters connected to respective ones of said voltage supply lines and their collectors connected together to said output node, and transistor-resistor bias circuitry connected to the bases of said output transistors to bias one of said output transistors to increase its current flow and the other output transistor to reduce its current flow in response to a change in the gain stage voltage output,
• said bias circuitry including a first level shifting resistor connected between the gain stage output and the base of one of said output transistors, a bias inversion circuit connected to supply a bias signal to the base of the other output transistor, and a second level shifting resistor connected between the gain stage output and said bias inversion circuit, said bias inversion circuit biasing said other output transistor to change its current flow in a direction opposite to said one output transistor in response to a change in the level shifted signal it receives from said second level shifting resistor,
• said bias inversion circuit including a pair of differentially connected bias transistors, with one bias transistor receiving a control input from said second level shifting resistor and the other bias transistor providing a current reference for a current mirroring transistor, said current mirroring transistor supplying the current for another transistor that is connected to be current mirrored by said other output transistor.