Method of providing electrical interconnect between two layers within a silicon substrate, semiconductor apparatus, and method of forming apparatus for testing semiconductor circuitry for operability

A semiconductor apparatus comprising:

• a substrate having a region of monocrystalline silicon, the monocrystalline silicon having a plurality of atoms with each being oriented in a plurality of different plane types;
• the region of monocrystalline silicon having a high elevation area and a low elevation area which are laterally angled relative to one another, the high elevation area being parallel with one of the plane types;
• the high elevation area and the low elevation area being interconnected by a substantially planar, non-perpendicularly angled surface;
• the angled surface extending substantially parallel with another of the plane types;
• and
• the high elevation area, the angled surface and the low elevation area having a continuously electrically conductive and interconnecting diffusion region of a first conductivity type extending from the high elevation area, through and along the angled surface to the low elevation area.

A semiconductor processing method of forming an electrically conductive projection outwardly extending from a substrate, the method comprising the following steps:

• providing a substrate having an outer region of monocrystalline silicon;
• epitaxially growing an electrically conductive layer of monocrystalline silicon from the outer region, the epitaxially grown layer being doped during growth with conductivity enhancing impurity of a first conductivity type;
• and
• etching the grown monocrystalline silicon layer to produce an outwardly projecting electrically conductive pillar.

A method of forming a testing apparatus for engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof, the method comprising the following steps:

• providing a locally substantially planar outer surface of electrically conductive polysilicon on a monocrystalline silicon substrate;
• providing a layer of masking material atop the substantially planar outer surface of electrically conductive polysilicon, the masking material being of different composition from the electrically conductive polysilicon such that the material is capable of substantially masking the electrically conductive polysilicon;
• patterning and etching the layer of masking material to selectively outwardly expose the electrically conductive polysilicon and define a grouping of discrete masking blocks, the discrete masking blocks of the grouping having respective centers, the respective centers of the grouping being positioned in sufficient proximity to one another such that the centers of the grouping fall within confines of a given single test pad which the apparatus is adapted to electrically engage;
• forming projecting apexes in the electrically conductive polysilicon beneath the masking blocks at the masking block centers, the projecting apexes forming a group falling within the confines of the given single test pad of which the apparatus is adapted to electrically engage;
• removing the discrete masking blocks from the electrically conductive polysilicon after the exposing step;
• and
• etching the electrically conductive polysilicon selectively relative to the underlying monocrystalline silicon to form an electrically conductive engagement probe.