US 5,418,973 AGranted

Digital computer system with cache controller coordinating both vector and scalar operations

AssigneeDigital Equipment Corporation

InventorsJames P. Ellis, Era Nangia, Nital Patwa, Bhavin Shah, Gilbert M. Wolrich

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Abstract

A digital computer system includes a scalar CPU, a vector processor, and a shared cache memory. The scalar CPU has an execution unit, a memory management unit, and a cache controller unit. The execution unit generates load/store memory addresses for vector load/store instructions. The load/store addresses are translated by the memory management unit, and stored in a write buffer that is also used for buffering scalar write addresses and write data. The cache controller coordinates-loads and stores between the vector processor and the shared cache with scalar reads and writes to the cache. Preferably the cache controller permits scalar reads to precede scalar writes and vector load/stores by checking for conflicts with scalar writes and vector load/stores in the write queue, and also permits vector load/stores to precede vector operates by checking for conflicts with vector operate information stored in a vector register scoreboard. Preferably the cache controller includes vector logic which is responsive to vector information written in intra-processor registers by the execution unit. The vector logic keeps track of the vector length and blocks extra memory addresses generated by the execution unit for the vector elements. The vector logic also blocks the memory addresses of masked vector elements so that these addresses are not translated by the memory management unit.

A digital computer system comprising, in combination:

a scalar central processing unit;
a vector processor;
and
a cache memory coupled to said scalar central processing unit for scalar reads and writes between said scalar central processing unit and said cache memory, and coupled to said vector processor for vector loads and stores between said vector processor and said cache memory;
wherein said scalar processing unit includes:
(a) an execution unit for executing scalar instructions and for issuing vector instructions to said vector processor,
(b) a memory management unit for translating virtual addresses of both said scalar instructions and said vector instructions to physical addresses, and
(c) a cache controller unit for coordinating data transfer between said scalar central processing unit and said cache memory;
and
wherein said execution unit includes means for computing virtual memory addresses of vector elements specified by vector load and vector store instructions and sending the virtual memory addresses to said memory management unit for translation to physical addresses,
wherein said cache controller unit includes means for coordinating both:
(a) vector loads and stores between said vector processor and said cache memory, and
(b) scalar reads and writes between said scalar central processing unit and said cache memory;
and
wherein said cache controller unit, said cache memory, and said vector processor are directly connected together by a common address bus and a common data bus;
wherein said cache controller unit includes a write queue for queuing both:
(a) scalar physical write addresses and scalar write data, and
(b) physical addresses of said vector elements of said vector store instructions;
and
means for servicing said write queue by addressing said cache memory with said scalar physical write addresses in said write queue for scalar operations and by addressing said cache memory for vector operations with said physical addresses of said vector elements in said write queue.

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Abstract

Claims7