Electrostatic discharge protection

An electrostatic discharge protection in an integrated circuit, comprising;

• (a) a semiconductor layer having a plurality of interconnected field effect transistors including a first field effect transistor, an input/output terminal and a first reference voltage terminal;
• (b) the first field effect transistor having a source, a drain, a channel disposed between the source and drain and a gate disposed over the channel and insulated therefrom, the source coupled to the input/output terminal, the drain coupled to the reference voltage terminal and the gate and drain coupled together to form a first ESD protection diode, said first ESD protection diode having a protection diode breakdown voltage between the drain and the channel greater than the reference voltage;
• (c) a first Zener region abutting the drain region of said first transistor to form a Zener diode having a Zener breakdown voltage less than the protection diode breakdown voltage and greater than the reference voltage for coupling the first input/output terminal through the channel of the first field effect transistor to the first reference voltage terminal during Zener breakdown;
• (d) a NPN bipolar transistor formed in said semiconductor layer, and
• (e) wherein said first Zener region has the doping profile of a base of said NPN transistor.

An electrostatic discharge protection in an integrated circuit, comprising;

• (a) a semiconductor layer having a plurality of interconnected field effect transistors including a first field effect transistor, an input/output terminal and a first reference voltage terminal;
• (b) the first field effect transistor having a source, a drain, a channel disposed between the source and drain and a gate disposed over the channel and insulated therefrom, the source coupled to the input/output terminal, the drain coupled to the reference voltage terminal and the gate and drain coupled together to form a first ESD protection diode, said first ESD protection diode having a protection diode breakdown voltage between the drain and the channel greater than the reference voltage;
• (c) a first Zener region abutting the drain region of said first transistor to form a Zener diode having a Zener breakdown voltage less than the protection diode breakdown voltage and greater than the reference voltage for coupling the first input/output terminal through the channel of the first field effect transistor to the first reference voltage terminal during Zener breakdown;
• (d) a PNP bipolar transistor formed in said semiconductor layer, and
• (e) wherein said first Zener region has the doping profile of a base of said PNP transistor.

An integrated circuit, comprising:

• (a) a semiconductor layer having a plurality of NMOS transistors formed in the semiconductor layer, a first input/output terminal and a first reference voltage terminal, each of said NMOS transistors with a N+ source region and a N+ drain region in a P region;
• and
• (b) a first ESD protection diode formed in said semiconductor layer and connected between said first input/output terminal and said first reference voltage terminal, said diode including a first NMOS transistor having a N+ source, a N+ drain, a P channel disposed between the source and drain and a gate disposed over the P channel and insulated therefrom, the source coupled to the input/output terminal, the drain coupled to the first reference voltage terminal and the gate and drain coupled together to form a first ESD protection diode, said first ESD protection diode having a protection diode breakdown voltage between the drain and the channel greater than the reference voltage;
• (c) a first Zener region abutting both said N+ drain region and said P channel region of said first NMOS transistor, said first Zener region of P type but more heavily doped than said P channel said first NMOS transistor to form a Zener diode having a Zener breakdown voltage less than the first protection diode breakdown voltage and greater than the reference voltage for coupling the first input/output terminal through the channel of the first NMOS transistor to the first reference voltage terminal during Zener breakdown.