Multi-level conductor process in VLSI fabrication utilizing an air bridge
AssigneeUnited Microelectronics Corp.
InventorsWater Lur, Jiunn Y. Wu
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Abstract
This invention deals with the formation of the multi-level electrode metal structure and the interconnecting inter-level metal studs used in the fabrication of VLSI circuits. After the metal layers have been formed the inter-level dielectric material used in forming the structure is etched away leaving an air dielectric between the levels. The electrode metal and the inter-level metal studs are coated with a thin envelope oxide and the entire structure is covered with a passivation layer using material with a poor step coverage. The structure of this invention provides reduced parasitic capacitance, better step coverage in interconnecting layers, and improved circuit performance.
Claims12
A method of forming a multi-level conductor structure for VLSI circuits, comprising the steps of:
- providing a silicon substrate with circuits formed therein, a base dielectric layer formed on said substrate, and contact studs formed in said base dielectric layer making electrical contact with said circuits;
- forming a first electrode metal layer on said base dielectric layer and contact studs;
- etching a first electrode pattern in said first electrode metal layer;
- forming a first thin envelope oxide layer on said first electrode pattern and said base dielectric layer;
- forming a first inter-metal dielectric layer over said thin envelope oxide layer;
- forming a second thin envelope oxide layer over said first inter-metal dielectric layer;
- etching first inter-level vias with sidewalls in said first inter-metal dielectric layer, said first thin envelope oxide layer, and said second thin envelope oxide layer;
- forming a thin envelope oxide spacer on said sidewalls of said first inter-level vias;
- filling said first inter-level vias with first inter-level metal studs;
- forming a second electrode metal layer on said second thin envelope oxide layer and said first inter-level metal studs;
- forming a third thin envelope oxide layer on said second electrode metal layer;
- etching a second electrode pattern in said second electrode metal layer, said second envelope oxide layer, and said third envelope oxide layer said second electrode pattern having sidewalls;
- forming a thin envelope oxide spacer on said sidewalls of said second electrode pattern;
- removing all said inter-metal dielectric;
- and
- forming a passivation layer with poor step coverage over said silicon substrate.
Dependencies are inferred from the claim text.