Parallel operation linear feedback shift register

A Multiple Input Shift Register (MISR) for generating a signature from a plurality of data-in signals, comprising:

• register means for storing data, said register means comprising a plurality of latches, wherein at least one of said latches is driven by a clock;
• a plurality of sequentially connected, functional equivalent combinatorial logic networks, one of said networks driving said register means, said register means driving a second of said networks to provide a feedback path, each of said networks generating a signature;
• and
• means for receiving a plurality of data-in signals at each of said combinatorial logic networks and for receiving one of said generated signatures, such that one of said generated signatures is combined with said data-in signals to generate a new signature.

A Linear Feedback Shift Register (LFSR) for generating random test patterns, comprising:

• a register for storing data, said register comprising a plurality of latches, wherein each said latch is driven by an external clock;
• a plurality of multiplexers (MUXs), each of said MUXs drives one said latch and is provided with two data and one control inputs, the first of said data inputs is a feedback line linking the output of the latch said MUX is driving back into said MUX to inhibit data stored in said latch from being altered, and said control input for providing a signal that selects which data is to appear at the output of said MUX;
• a plurality of exclusive-OR circuits (XORs), which number equals the number of said latches, wherein each said XORs subsequent to the first said XORs links one said latches to the next adjacent one via a first data input, wherein the output of each said XORs is connected to the second said two data inputs of said MUX to maintain normal operation of the LFSR, and wherein the first input of the first said XORs for providing data to the first said latches;
• and
• a plurality of dual input AND gates which number is equal to the number of XORs, wherein the output of each said AND gates is connected to said second data input of said XOR, the first of said dual inputs of each said AND gates is connected to the output of the last stage of said register, and the second said dual inputs is respectively connected to one of a plurality of external lines, wherein binary values on said external lines dynamically reconfigure the LSFR by selectively adding a signal from said output of said last latch of said register.

A Linear Feedback Shift Register (LFSR) provided with fixed configuration capabilities, comprising:

• a register for storing data, comprising a plurality of latches, wherein each said latch is driven by an external clock;
• a plurality of multiplexer circuits (MUXs), each said MUXs drives one of said latches and is provided with two data and one control inputs, the first of said data inputs is a feedback line tying the output of the latch said MUX is driving back into said MUX to inhibit test data stored in said latch from being altered, and said control input is a line for providing a signal that selects which data input will appear at the output of said MUX;
• a plurality of exclusive-OR circuits (XORs), in which the number of said XORs is less than the number of said latches in said register, wherein each said XORs links one said latches to the next adjacent one via a first data input, the output of the last said latches of said register provides a second data input to each said XORs, wherein the output of each said XORs is connected to the second said two data inputs of said MUX to maintain normal operation of the LFSR,
• wherein the second input of the first said MUXs is provided by the output of the last said latches, and
• such that in the absence of one of said XORs connected to one of said MUXs, the output of the previous latch in said register is directly connected to said second data input of said MUX so that test data stored in each of said latches is selectively modified when test data shifts from one of said latches to the next one.

A Multiple Input Shift Register (MISR) for generating a signature from plural data-in signals, comprising:

• a register for storing data, said register comprising a plurality of latches, wherein each said latch is driven by an external clock;
• a plurality of multiplexer circuits (MUXs), each said MUXs drives one of said latches and is provided with two data and one control inputs, the first of said data inputs is a feedback line linking the output of the latch said MUX is driving back into said MUX to inhibit test data stored in said latch from being altered, and said control input for providing a signal that selects which data input will appear at the output of said MUX;
• a plurality of exclusive-OR circuits (XORs), which number equals the number of said latches, for generating a signature, wherein each said XORs subsequent to the first said XORs links one said latches to the next adjacent one via a first data input, wherein the output of each said XORs is connected to the second said two data inputs of said MUX to maintain normal operation of the MISR, wherein the first input of the first said XORs provides data to the first said latches, and wherein at least one of said XORs is provided with a third input for providing data;
• and
• a plurality of dual input AND gates which number is equal to the number of XORs, such that the output of each said AND gates is connected to said second data input of said XOR, the first of said dual inputs of each said AND gates is connected to the output of the last stage of said register, and the second said dual inputs is respectively connected to a line, wherein a binary value on said line dynamically reconfigures the MISR by selectively adding a signal from said output of said last latch of said register.