Non-volatile semiconductor memory device capable of storing multi-value data in each memory cell

An electrically erasable non-volatile semiconductor memory device comprising:

• a plurality of row lines and column lines;
• a plurality of memory cells connected in a matrix to said plurality of row lines and column lines;
• selection means for selecting a desired one of said plurality of memory cells;
• write-control means for writing data into said plurality of memory cells, said write-control means including means for producing a plurality of different signals, and means for selecting one of said different signals according to a data signal externally applied thereto and applying said selected one of said different signals to said selected memory cell;
• and
• read-control means for reading out data written into said selected memory cell and converting the data read-out from said selected memory cell into an output data signal corresponding to the data signal applied to said write-control means.

An electrically erasable non-volatile semiconductor memory device comprising:

• a plurality of row lines and column lines;
• a plurality of memory cells connected in a matrix to said plurality of row lines and column lines;
• selection means for selecting a desired one of said plurality of memory cells;
• write-control means for writing data into said plurality of memory cells, said write-control means including means for presetting at least four different pulse signals of different pulse numbers, means for selecting one of said four different pulse signals according to a data signal externally applied thereto and applying said selected pulse signal to said selected memory cell;
• and
• read-control means for reading out data written into said selected memory cell and converting the data read-out from said selected memory cell into a data signal corresponding to one of said four pulse signals.

An electrically erasable non-volatile semiconductor memory device comprising:

• a plurality of row lines and column lines;
• a plurality of electrically erasable memory cells connected in a matrix to said plurality of row lines and column lines, each memory cell being settable at at least four different threshold values;
• a plurality of address input terminals;
• a plurality of address buffer circuits connected to said address input terminals, respectively, for receiving address signals through said input terminals;
• a plurality of control terminals;
• decoder means for selecting one of said row lines and one of said column lines based on outputs of said address buffer circuits, thereby selecting one of said plurality of memory cells;
• data input buffer means for receiving a data signals to be written into said memory cells;
• data output buffer means for outputting a data signal written in said selected one memory cell;
• a program circuit for producing at least four different voltage signals corresponding to said at least four different threshold values, selecting one of said at least four different voltage signals based on an output of said data input buffer means and setting said selected one memory cell at one of said threshold values corresponding to said selected voltage signal, thereby writing the data signal into said selected memory cell;
• and
• a sense circuit for detecting the threshold value of said selected memory cell as an electrical signal from said selected column line, converting said threshold value into a corresponding data signal and outputting said converted data signal to said data output buffer means.