Wavefront array processor for blocking the issuance of first handshake signal (req) by the presence of second handshake signal (ack) which indicates the readyness of the receiving cell

A multiple-instruction, multiple-data-stream wavefront array processor having a plurality of cells, wherein each cell can receive data, process data and transmit data, said cells arranged in a mesh and interconnected by a network, comprising external bus means for communicating with a host;

• bus switch means for coupling said external bus means to cells located at one or more edges of said array processor;
• and each one of said cells comprising:
• at least four handshake ports, each said handshake port functioning to transfer data over said network to and from an adjacent cell, and including
• handshaking means coupled to said handshake port for exchanging handshaking signals with an adjacent cell, wherein said handshaking signals include a first handshake signal, which indicates that said cell is ready to transmit data to said adjacent cell, a second handshake signal which indicates that said cell is not ready to receive transmitted data from said adjacent cell, and wherein said cell transmits said data with said first handshake signal, but only when said adjacent cell is not sending said second handshake signal to said cell,
• transmitting means, coupled to said handshaking means for transmitting said data over said network to said adjacent cell, and
• a FIFO buffer coupled to said handshaking means for receiving and buffering said data transmitted over said network from said adjacent cell, said FIFO buffer providing a sink status signal being indicative that said FIFO buffer is not full thereby causing said second handshake signal to be suppressed, wherein said handshaking means operates to enable the transmission of data to said FIFO buffer during an absence of said second handshake signal;
• and said FIFO buffer providing a second sink status signal determined by said buffered data being indicative that said FIFO buffer is empty;
• data processing means coupled to said transmitting means and said FIFO buffer, for accessing and processing said transmitted data received by said receiving means, and providing said transmitting means with data, said data processing means providing a source status signal to said transmitting means indicative of whether said data processing means has data to be transmitted or said receiving means has data to be transmitted to said adjacent cell, and where said first handshake signal is responsive to said source status signal;
• a ring bus having first and second rings connected to an input of said transmitting means and an output of said FIFO buffer of each one of said handshake ports, and a third ring connected to an input of said transmitting means of each one of said handshake ports;
• a first source bus connected to said first ring;
• a second source bus connected to said second ring;
• a result bus connected to said third ring;
• and
• an arithmetic logic unit having a first input connected to said first source bus, a second input connected to said second source bus, and an output connected to said result bus;
• and
• a first blocking means coupled to said FIFO buffer and responsive to said second sink status signal, for blocking said FIFO buffer from receiving said transmitted data from said adjacent cell, when said second status signal is not present;
• and
• a second blocking means coupled to said transmitting means and responsive to said second handshake signal, for blocking said data processing means from providing data to said transmitting means, for blocking said receiving means from providing data to said transmitting means and for blocking said transmitting means from transmitting data to said adjacent cell, when said adjacent cell sends said second handshake signal to said cell.