PLL frequency synthesizer circuit

A phase locked loop frequency synthesizer circuit for detecting and generating a signal locked to a predetermined frequency, the phase locked loop frequency synthesizer circuit comprising:

• a voltage controlled oscillator providing an oscillating signal;
• a clock providing a clocked signal;
• reference frequency dividing means, coupled to the clock, for dividing the clocked signal into a reference frequency signal having a first frequency and a first phase;
• comparison frequency divider means, coupled to the voltage controlled oscillator, for receiving the oscillating signal and dividing said oscillating signal into a comparison signal having a second frequency and a second phase, said comparison frequency divider means comprising;
• prescaler circuit means, coupled to the voltage controlled oscillator, for dividing the oscillating signal into a divided signal having a third frequency, and
• a comparison frequency divider, coupled to the prescaler circuit means, receiving the divided signal, dividing the divided signal, and transmitting the comparison signal;
• a phase comparator, coupled to the reference frequency dividing means and to the comparison frequency divider means, detecting a phase difference between the first phase of the reference frequency signal and the second phase of the comparison signal and transmitting a phase difference signal in response to the phase difference;
• a first charge pump, coupled to the phase comparator, transmitting a first voltage signal in response to the phase difference signal from the phase comparator;
• a low pass filter, coupled to the first charge pump and to the voltage controlled oscillator, smoothing out the first voltage signal from the first charge pump to remove high frequency components therefrom, the low pass filter generating a controlled voltage signal and transmitting the controlled voltage signal to the voltage controlled oscillator;
• and
• a frequency lock determining circuit, coupled to the reference frequency dividing means and to the comparison frequency divider means, comparing the first frequency of the reference frequency signal with the second frequency of the comparison signal and generating a frequency difference, said frequency lock determining circuit transmitting a lock detecting signal if the frequency difference between the first frequency and the second frequency is within a preset value range, and transmitting an unlock detecting signal if the frequency difference between the first frequency and the second frequency exceeds the preset value range, said frequency lock determining circuit comprising;
• a first frequency comparator, coupled to the reference frequency dividing means and to the comparison frequency divider means, receiving the reference frequency signal and the divided signal, and transmitting a first detection signal if the third frequency of the divided signal is higher than the first frequency of the reference frequency signal,
• a second frequency comparator, coupled to the comparison frequency divider means and to the clock, receiving the clocked signal and the comparison signal and for transmitting a second detection signal if a frequency of the clocked signal is higher than the second frequency of the comparison signal, and
• a frequency determination circuit, coupled to the first frequency comparator and to the second frequency comparator, transmitting the unlock detecting signal when at least one of the first and second detection signals is transmitted from the first and second frequency comparators.