Delay line loop for on-chip clock synthesis with zero skew and 50% duty cycle

A microprocessor system with a central processing unit (CPU) and peripheral units driven by a common reference clock wherein the CPU comprises:

• (a) an arithmetic and logic processor operating synchronously with a CPU clock signal;
• and
• (b) a synchronous clock generator with an input connected to an externally supplied common reference clock for synthesizing a 50% duty cycle CPU clock signal synchronized with the externally supplied common reference clock, the synthesized CPU clock, connected to the arithmetic processor input, having an integer number of periods per common reference clock period, each clock signal having a first state following a first transition, and a second state following a second transition during each of their respective clock periods, comprising:
• (i) a controllable delay line with a nominal delay of one half of a period of the synthesized CPU clock for accepting the synthesized CPU clock signal at its input and producing a delayed replica at its output;
• (ii) a delay line control loop comprising a controllable delay line controller coupled to the controllable delay line for producing at the delay line output a synthesized CPU clock waveform with its first transition synchronous with a corresponding first transition of the reference clock signal, the delay of the controllable delay line controlled by the controllable delay line controller by comparing the reference clock first transition with a corresponding first transition of the synthesized CPU clock waveform at the output of the delay line;
• and
• (iii) a clock waveform generating loop comprising a clock waveform generator with its output connected to the input of the controllable delay line for synthesizing a 50% duty cycle waveform by selecting the first transition of the reference clock signal, inverting and delaying the first reference clock transition through the delay line for a half-period of the synthesized CPU clock, this inverted and delayed first transition of the reference clock signal being representative of the synthesized CPU clock second transition at the output of the controllable delay line, selecting and inverting the second transition of the synthesized CPU clock at the controllable delay line output as an input to the delay line so that after being delayed by the controllable delay line it is representative of a new first transition of the synthesized CPU clock, repeating this process until a prescribed even number of synthesized CPU clock half-periods elapse so that the next reference clock transition is selected and inverted thereby repeating the synthesizing process and generating a periodic, 50% duty-cycle, synthesized CPU clock waveform at the output of the delay line having an integer number of cycles for each reference clock cycle.

A method for synthesizing a local clock signal that is synchronized with an external reference clock signal, the synthesized clock signal having a 50% duty cycle independent of the external clock duty cycle, the synthesized clock having an integer number of periods, N, for each period of the reference clock, each of the clocks having a periodic first state following a periodic first transition, and a periodic second state following a periodic second transition during each clock period, the synthesizing steps comprising:

• a) generating a synthesized clock first transition coincident with the first reference clock transition and generating a synthesized clock first state following the first transition;
• b) delaying the synthesized clock first transition and state by a controllable delay interval nominally corresponding to 1/2N of the reference clock period;
• c) inverting the delayed synthesized clock first transition and state for producing a synthesized clock second transition and state;
• d) delaying the synthesized clock second transition and state by the predetermined nominal delay of 1/2N of the reference clock period;
• e) inverting the delayed synthesized clock second transition and state for producing a synthesized clock first transition and state;
• f) repeating steps (b) through (e) until the next reference clock first transition occurs;
• g) comparing the next reference clock first transition with the corresponding synthesized clock transition that nominally occurs after every N synthesized clock periods;
• h) adjusting the controllable delay interval so that N periods of the synthesized clock corresponds to the reference clock period;
• and
• i) repeating steps a) through h).