Method for optimizing the structure of a transistor to withstand electrostatic discharge

A method for determining an optimal structure for an insulated gate field effect transistor on a semiconductor integrated circuit that best resists damage from electrostatic discharge, said method comprising the steps of:

• (a) Initializing test equipment with specific test conditions for testing a plurality of insulated gate field effect transistors on a semiconductor integrated circuit, each of the insulated gate field effect transistors having at least one different structural dimension than the other field effect transistors;
• (b) measuring a first leakage current of each of the field effect transistors;
• (c) pulsing each of the field effect transistors with a pulse having a predefined voltage amplitude and time duration;
• (d) measuring a plurality of current and voltage values of each field effect transistor during its respective pulse;
• (e) calculating dynamic resistance for each field effect transistor from the respective measured plurality of current and voltage values;
• (f) measuring a second leakage current of each field effect transistor after pulsing the field effect transistor;
• (g) storing the plurality of current and voltage values, dynamic resistance, and first and second leakage currents of each field effect transistor;
• (h) increasing the pulse voltage amplitude and repeating steps (c) through (h) for each field effect transistor until the measured second leakage current of each of the field effect transistors changes a predetermined amount, then storing each of the last measured pulse voltage amplitude values for each field effect transistor as a failure voltage value for the respective field effect transistor;
• and
• (i) selecting the field effect transistor having the highest failure voltage value in order to determine an optimal field effect transistor structure resistant to damage from electrostatic discharge.