Circuitry and method for sense amplification

Circuitry for sense amplification, comprising:

• input circuitry for inputting a differential input voltage on first and second input voltage paths;
• output circuitry for outputting a differential output voltage;
• reset circuitry including a reset signal line, said reset circuitry being coupled to said output circuitry for substantially minimizing said differential output voltage when a reset signal appears on said reset signal line;
• bias circuitry coupled between said input circuity and said output circuitry for producing a bias voltage which affects said differential output voltage at said reset signal in response to said differential input voltage;
• and
• amplification circuitry coupled to said bias circuitry and to said output circuitry for amplifying said differential output voltage after said reset signal in response to said bias voltage, said amplification circuitry comprising first and second inverters, an output of said first inverter being coupled to an input of said second inverter and an output of said inverter being coupled to an input of said first inverter, such that said first and second inverters form a positive feedback loop, said first inverter comprising a first N channel transistor and a first P channel transistor, wherein said second inverter comprises a second N channel transistor and a second P channel transistor, wherein gates of said first N channel and P channel transistors are coupled to a first node, and wherein gates of said second N channel and P channel transistors are coupled to a second node, said bias circuitry comprising an additional field effect transistor having a gate coupled to a first voltage source, a first source/drain coupled to sources of said first and second N channel transistors, and a second source/drain coupled to a second voltage source, such that said additional field effect transistor provides a bias current through said first and second inverters in order to assist said biasing.

A method of sense amplification, comprising the steps of:

• inputting a differential input voltage;
• outputting a differential output voltage, said outputting step comprising the step of outputting said differential output voltage on respective first and second outputs of first and second inverters in response to voltages of first and second nodes, wherein respective first and second inputs of said first and second inverters are coupled respectively to said first and second nodes;
• substantially minimizing said differential output voltage when a reset signal appears on a reset signal line, said substantially minimizing step comprising the step of providing low impedance paths between a voltage source and said first and second nodes during said reset signal;
• providing a bias voltage for affecting said differential output voltage at said reset signal in response to said differential input voltage;
• amplifying said differential output voltage after said reset signal in response to providing a bias voltage.

Circuitry for sense amplification, comprising:

• a first inverter having an input coupled to a first node and an output coupled to a second node, said first inverter including first and second transistors having source/drain current paths coupled in series, said first and second transistors having gates coupled to said first node;
• a third transistor having a gate for receiving a first input signal, a source/drain current path coupled between said source/drain current paths of said first and second transistors, and a first source/drain coupled to said second node;
• a second inverter having an input coupled to said second node and an output coupled to said first node, said second inverter including fourth and fifth transistors having source/drain current paths coupled in series, said fourth and fifth transistors having gates coupled to said second node;
• a sixth transistor having a gate for receiving a second input signal, a source/drain current path coupled between said source/drain current paths of said fourth and fifth transistors, and a first source/drain coupled to said first node;
• and
• reset circuitry responsive to a first state of a clock signal for coupling said first and second nodes to a first voltage source.