Adaptive analog minimum/maximum selector and subtractor circuit

A multi-channel minimum selector and subtractor circuit, including:

• a plurality of input nodes;
• a plurality of output nodes;
• a plurality of current sources
• a common conductive line;
• a plurality of P-Channel MOS transistors, each of said P-Channel MOS transistors having a gate connected to a different one of said input nodes, a source connected to a different one of said current sources, and a drain;
• a plurality of N-Channel MOS transistors, each of said P-Channel MOS transistors having a drain connected to the drain of said P-Channel MOS transistor, a source connected to a fixed voltage source and a gate connected to a current limit bias source;
• a plurality of first switches, each of said first switches connected between said common conductive line and the source of one of a different one of said P-Channel transistors;
• a plurality of transconductance amplifiers, each of said transconductance amplifiers having an output connected to a different one of said output nodes, an inverting input, and a non-inverting input connected to the source of a different one of said P-Channel MOS transistors;
• a plurality of capacitors, each of said capacitors connected between a fixed voltage source and the inverting input of a different one of said transconductance amplifiers;
• a plurality of second switches, each of said second switches connected between the output and the inverting input of a different one of said transconductance amplifiers;
• and
• means for opening all of said first and second switches during a first operating phase of said minimum selector and subtractor circuit, and for closing all of said first and second switches during a second operating phase of said minimum selector and subtractor circuit.

A multi-channel maximum selector and subtractor circuit, including:

• a plurality of input nodes;
• a plurality of output nodes;
• a plurality of current sinks
• a common conductive line;
• a plurality of N-Channel MOS transistors, each of said N-Channel MOS transistors having a gate connected to a different one of said input nodes, a source connected to a different one of said current sinks, and a drain connected to a fixed voltage source at a potential more positive than the potential at said source of said N-Channel MOS transistor;
• a plurality of first switches, each of said first switches connected between said common conductive line and the source of one of a different one of said N-Channel transistors;
• a plurality of transconductance amplifiers, each of said transconductance amplifiers having an output connected to a different one of said output nodes, an inverting input, and a non-inverting input connected to the source of a different one of said N-Channel MOS transistors;
• a plurality of capacitors, each of said capacitors connected between a fixed voltage source and the inverting input of a different one of said transconductance amplifiers;
• a plurality of second switches, each of said second switches connected between the output and the inverting input of a different one of said transconductance amplifiers;
• and
• means for closing all of said first and second switches during a first operating phase of said maximum selector and subtractor circuit, and for opening all of said first and second switches during a second operating phase of said maximum selector and subtractor circuit.

A multi-channel maximum selector and subtractor circuit, including:

• a plurality of input nodes;
• a plurality of output nodes;
• a plurality of current sinks;
• a common conductive line;
• a plurality of N-Channel MOS transistors, each of said N-Channel MOS transistors having a gate connected to a different one of said input nodes, a source connected to a different one of said current sinks, and a drain;
• a plurality of P-Channel MOS current-limiting transistors, each of said P-Channel MOS transistors having a drain connected to the drain of said N-Channel MOS transistor, a source connected to a fixed voltage source and a gate connected to a current-limit bias source;
• a plurality of first switches, each of said first switches connected between said common conductive line and the source of one of a different one of said P-Channel transistors;
• a plurality of transconductance amplifiers, each of said transconductance amplifiers having an output connected to a different one of said output nodes, an inverting input, and a non-inverting input connected to the source of a different one of said P-Channel MOS transistors;
• a plurality of capacitors, each of said capacitors connected between a fixed voltage source and the inverting input of a different one of said transconductance amplifiers;
• a plurality of second switches, each of said second switches connected between the output and the inverting input of a different one of said transconductance amplifiers;
• and
• means for closing all of said first and second switches during a first operating phase of said maximum selector and subtractor circuit, and for opening all of said first and second switches during a second operating phase of said maximum selector and subtractor circuit.