Chemical mechanical polishing slurry delivery and mixing system

#Chemical mechanical polishing (CMP) techniques are used in the semiconductor industry to remove metals from semiconductor surfaces. One common use of these techniques is to remove that portion of a layer of tungsten or other metal which overlies an interlayer dielectric glass such as phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphocilicate glass (BPSG) or silicon dioxide (SiO.sub.2), so as to form plugs within the layer of dielectric. First, openings are formed within the dielectric layer. A layer of metal is then deposited so as to fill the openings and to form an overlying layer of metallization. The metal layer is then polished until the layer of metallization which overlies the dielectric is removed. The portion of the metal layer which fills the vias remains, forming metal fill areas. Fill areas are often referred to as being either "vias" or "plugs" depending on the material to be contacted. However, in the present application, all fill areas will be referred to as "plugs" irrespective the material to be contacted.

#Prior art processes for removing the overlying layer of metallization have included standard dry etches. Prior art dry etch steps typically leave etch residue, metal particles, or metal islands remaining on the ILD glass surface. They can also leave a mottled or pitted glass surface due to the tungsten dry etch chemistry attacking the glass. In addition, dry etches can over-etch plugs so as to form excessive plug recess, concave non uniformly etched plugs, and etch-out of the metal/glass side wall interface.

#In order to overcome these disadvantages manufactures have used chemical mechanical polishing (CMP) to remove the overlying layer of metallization. Prior art techniques for chemical mechanical polishing have involved the use of premixed bulk slurry chemicals. The metal polishing bulk slurries formed using these chemicals tend to agglomerate or gel quickly and foul up the slurry delivery plumbing of the polishing apparatus. Consequently, the use of premixed bulk slurry chemicals can often lead to unevenly polished surfaces. Also, the pH levels required to keep the premixed bulk slurries from gelling can alter the metal polishing rate and selectivity to the dielectric such that over-etch of the plug results. Other problems with the use of bulk slurries are the fact that polishing equipment delivery systems may corrode rapidly, dynamic changes of slurry chemistry are not feasible, and the fact that most premixed slurries are not within the limited ranges of slurry mixtures which are effective. This limited range for premixed slurries is primarily due to the delicate balance needed between the chemical stability of slurry and the ability of the slurry to polish metal. What is needed is a process for generating CMP slurry that has a wide pH range, will not gel, and will not form chemical precipitates but will provide the right balance of polishing and etching which creates a smooth, planar glass surface and uniform plug surface while maintaining a high metal removal rate and high selectively between the metal and glass dielectric.

#The present invention will now be described with reference to a preferred embodiment in which:

#FIG. 1 illustrates a cross section of a portion of a wafer surface having an dielectric layer in which a plurality of openings have been formed.

#FIG. 2 illustrates the structure of FIG. 1 upon which a layer of metal has been deposited.

#In the following descriptions, numerous specific details such as dimensions, specific chemical components and delivery methods, etc. are described in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that the present invention can be practiced without these specific details. In other instances, well known method steps have not been described in detail in order not to unnecessarily obscure the present invention.

#FIG. 1 illustrates a cross section of a portion of a semiconductor wafer 100 upon which a diffusion region 101 has been formed. This diffusion region may be an N or P doped region and is formed by methods well known to those in the art. Dielectric S layers are then formed over the semiconductor surface. Dielectric region 103 is shown to overlie the wafer surface. Conductor 102 is then formed by depositing and patterning a layer of conductive material over the dielectric layer 103. The conductor 102 is usually formed from a metal which may be a combination of aluminum, titanium, and titanium nitride. Dielectric layer 104 is shown as overlying the conductor 102. This layer may be Polysilicate Glass (PSG), Silicon Dioxide or any number of other dielectric materials. Openings 105 and 106 are then etched so as to expose the diffusion region 101 and the conductor 102. Though opening 105 is shown to directly contact the diffusion region 101 it is well known in the art to form other layers or structures over the diffusion region. The contact may be to these overlying layers. For example, a silicide layer is typically formed over the diffusion region.

#FIG. 2 illustrates the structure shown in FIG. 1 after a conductive layer 201 has been deposited. This layer is typically formed by depositing a metal layer over the wafer surface. In the preferred embodiment of the present invention this metal layer is comprised of tungsten. This metal layer will fill openings 105 and 106 so as to form fill areas 202 and 203, and so as to overlie the top surface of dielectric layer 104.