US 5,406,630 A · Tamperproof arrangement for an integrated circuit device

Abstract

A tamperproof arrangement for an integrated circuit device. The arrangement includes a package and lid fabricated of heavy metals to prevent X-radiation or infrared detection of circuit operation. Sensors and control circuitry are located on the integrated circuit die itself which detect increased temperature and radiation and clear or zeroize any sensitive information included within the integrated circuit device. Electrode finger grids above and below the integrated circuit die detect physical attempts to penetrate the integrated circuit die. Critical circuit functions are segregated from non-critical functions. Power applied to the integrated circuit device is monitored and separated for critical and non-critical circuit functions.

Claims2

Dependent claims

A tamperproof method for an integrated circuit die comprising the steps of:

segregating critical circuit functions from non-critical circuit functions on said integrated circuit die;
locating said critical circuit functions substantially in the center of the integrated circuit die;
providing temperature sensors in said critical circuit area of said integrated circuit die to detect excessive temperature;
providing radiation sensors in said critical circuit area of said integrated circuit die to detect excessive radiation levels in said critical circuit area;
and
clearing all memory elements in said critical circuit function area, if excessive temperature or excessive radiation is detected by said temperature sensors or radiation sensors respectively.

3 more elements

Dependencies are inferred from the claim text.

Tamperproof arrangement for an integrated circuit device

Life of this patent

Tamperproof arrangement for an integrated circuit device

Life of this patent

Abstract

Claims2