Multi-threaded microprocessor architecture utilizing static interleaving

A method for compiling and executing one instruction thread from a plurality of instruction threads in a multi-threaded processor system, said processor system comprising a processor including a plurality of function units comprising,

• allocating said function units in accordance with an allocation vector for the execution of instructions from specific ones of said threads in specific fixed predetermined time slots in a fixed predetermined repeating pattern of time slots,
• utilizing queues to provide a fixed predetermined delay for each instruction so that each instruction is applied to the appropriate function unit in the appropriate predetermined time slot,
• utilizing a sequential compiler to compile a source program into a sequence of machine instructions which can be executed by particular function units in said processor system,
• utilizing a parallel compiler to reorganize said sequence of machine instructions into a sequence of patterns of instructions, each instruction having a location in a pattern of instructions depending on its data dependency with a previous instruction in said sequence of instructions and depending on said allocation vector which defines the time slots in which the appropriate function unit will be available to execute the instruction,
• utilizing said parallel compiler to compact the instructions of each pattern of instructions into a horizontal instruction word to form said one instruction thread,
• storing the instructions of said one instruction thread in a cache, and
• executing said instructions of said one instruction thread using said function units.

A method for concurrently executing a plurality of instruction threads in a multi-threaded processor including a plurality of function units and a cache system for storing horizontal instruction words comprising each of said threads, each horizontal instruction word containing one or more instructions to be executed by particular ones of said function units, said method comprising the steps of

• fetching from said cache system horizontal instruction words belonging to different ones of said threads at predetermined times and in a predetermined order,
• allocating each of said function units for the execution of an instruction from a particular thread in a fioxed predetermined time slot in a fixed predetermined repeating pattern of time slots,
• utilizing queues to provide a fixed predetermined delay for each instruction so that each instruction is applied to the appropriate function unit in the appropriate predetermined time slot, and
• executing said instruction in said horizontal instruction words by said function units in said allocated time slots.

A microprocessor for executing a plurality of instruction threads comprising

• a plurality of function units,
• a plurality of instruction caches, each for storing horizontal instruction words of one thread,
• a plurality of instruction fetch units for fetching horizontal instruction words from corresponding ones of said caches, and
• an allocator for allocating each of said function units for the execution of a machine instruction from a particular instruction thread in a fixed predetermined time slot in a repeating pattern of time slots in accordance with an allocation vector which minimizes read after write latencies in machine instructions in said horizontal instruction words, wherein said allocation means comprises queues for providing a fixed predetermined delay for each machine instruction in each of said horizontal instruction words in said instruction threads so that each machine instruction is applied to the appropriate function unit in the appropriate allocated time slot.