Method and apparatus for transferring data in portable image processing system

A microprocessor system suitable for the transfer of a block of image data units, comprising:

• a central processing unit (CPU);
• a data source device;
• a data destination device;
• at least one of the data source and data destination devices including a plurality of individually addressable data unit storage locations;
• a system bus, including a first set of data bus lines, a set of address bus lines, a set of control bus lines, electrically interconnecting the CPU, data source device and data destination device;
• a second set of data bus lines interconnecting the data source and data destination devices;
• and a transfer control signal line;
• an address register connected to the first set of data lines for receiving a starting address of sequentially addressable ones of the plurality of storage locations, and connected to specify a given one of the sequentially addressable ones of the storage location to be in data transfer communication with the second set of data bus lines;
• first "ready" signal means coupled to the data source device for signalling when the data source device is ready to transfer data to the second set of data bus lines;
• second "ready" signal means associated with the data destination device for signalling when the data destination device is ready to transfer data from the second set of data bus lines;
• means for delivering a transfer control signal to the transfer control signal line from the CPU;
• enabling means, connecting the transfer control signal line to the first and second "ready" signal means, for enabling the data source device to transfer a data unit to the data destination device through the second set of data bus lines in response to the simultaneous occurrence of the first "ready" signal, the second "ready" signal and the transfer control signal;
• means connected to the address register for incrementing the address stored in that register in response to transfer of a data unit from the data source to the data destination device;
• and
• means for signalling when all data units in the block have been transferred.

In a microprocessor system comprising a central processing unit (CPU), a memory and another device;

• the memory having a plurality of individually addressable data unit storage locations and the other device having at least one individually addressable data unit storage location;
• and the CPU, memory and other device being respectively electrically interconnected by a system bus, including a first set of data bus lines, a set of address bus lines and a set of control lines, so that a data unit can be transferred between the memory and the other device under control of the CPU in a process in which the data unit is read from a first addressed one of the storage locations of the memory or other device in accordance with a first address placed on the address bus lines, and then written to a second addressed one of the storage locations of the other device or memory in accordance with a second address placed on the address bus lines;
• the method of transferring a block of data units between sequentially addressed ones of the memory storage locations and the other device at least one storage location, the method comprising the steps of:
• providing a second set of data bus lines connecting the memory and the other device;
• using the first set of data bus lines, loading a starting address of the sequentially addressed ones of the memory storage locations into an address register;
• using the first set of data bus lines, loading a number corresponding to a total number of data units in the block into a count register;
• signalling a transfer control signal when the starting address and total number count have been loaded;
• signalling a first "ready" signal when the memory is ready to participate in a data unit transfer;
• signalling a second "ready" signal when the other device is ready to participate in a data unit transfer;
• in response to the simultaneous presence of all of the transfer control signal, first "ready" signal and second "ready" signal, enabling the transfer of a data unit between the memory storage location whose address is present in the address register and the at least one storage location, through the second set of data bus lines;
• incrementing the contents of the address and count registers;
• and
• repeating the enabling and incrementing steps until the contents of the count register indicates that the total number of data units in the block has been transferred.

A method for transferring a block of image data units, between a data source device and a data destination device of a microprocessor system, at least one of the data source and data destination devices including a plurality of individually addressable data unit storage locations;

• the system including a central processing unit (CPU), and a system bus having a first set of data bus lines, a set of address bus lines and a set of control bus lines electrically interconnecting the CPU, data source device and data destination device;
• and the data source device and data destination device each including a "ready" terminal for indicating a data transfer "ready" status;
• the method comprising:
• providing a second set of data bus lines electrically connecting the data source and data destination devices;
• and a transfer control signal line for signalling a transfer control signal;
• providing the data source device with an "enable output" terminal for receiving an "enable" signal to enable data transfer from the data source device to the second set of data bus lines;
• and the data destination device with an "enable input" terminal for receiving an "enable" signal to enable data transfer from the second set of data bus lines to the data destination device;
• and
• connecting the "ready," "enable output" and "enable input" terminals in an AND-gate arrangement to the transfer control line, so that the "enable" signals will be given only when "ready" signals are present at both "ready" terminals and the transfer control signal is present at the transfer control line.