Apparatus for quantizing pixel information to an output video display space

Quantization circuitry comprising:

• a bus having plurality of lines each for carrying a masking bit;
• an adder having a first plurality of inputs for receiving respective ones of plurality of parallel input pixel data bits, a second plurality of inputs, a saturation signal output and a plurality of data outputs;
• a first NOR gate having a first input coupled to a most significant bit one of said plurality of data outputs of said adder and a second input coupled to said saturation signal output of said adder;
• a first plurality of AND gates each having a first input coupled to said saturation output of said adder and a second input coupled to a respective one of said plurality of lines of said bus;
• a second plurality of NOR gates each having a first input coupled to an output of a corresponding one of said AND gates and a second input coupled to a corresponding lesser significant bit one of said plurality of data outputs of said adder;
• a register having a most significant bit input, a plurality of lesser significant bit inputs, a most significant bit output and a plurality of lesser significant bit outputs, said most significant bit input coupled to an output of said first NOR gate and said lesser significant bit inputs each coupled to an output of a respective one of said second plurality of NOR gates;
• a third plurality of NOR gates each having a first input coupled to a respective one of said plurality of lines of said bus, a second input coupled to a respective one of said plurality of lesser significant bit outputs of said register, and a output coupled to a respective one of said plurality of second inputs of said adder, said adder operable to add bits received at said plurality of second inputs of said adder with bits received at said plurality of first inputs of a said adder;
• a most significant bit output gate coupled to said most significant bit output of said register;
• and
• a plurality of lesser significant bit output AND gates each having a first input coupled to a respective line of said bus and a second inverting input coupled to a respective one of said plurality of lesser significant bit outputs of said register.