Telephone answering device with standardized internal bus
AssigneeTandy Corporation
InventorsRobert Sanford, Robert Cook, Gerald Stuteville
Life of this patent
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Abstract
The invention comprises a telephone answering device in which a microprocessor controller is coupled to all of the peripheral components through a single common multi-bit data/instruction bus and each peripheral component is coupled to the data bus through a latch which is enabled responsive to an enable instruction placed on a port of the controller.
Claims13
A telephone answering device comprising:
- a plurality of peripheral components for performing functions of said telephone answering device,
- a controller, including a plurality of controller bus ports and a separate latch-control port corresponding to each of said peripheral components, for generating at the controller bus ports data and instructions for controlling said peripheral components, for generating latch-disabling signals at the latch-control ports corresponding to the peripheral components for which the data and instructions have been generated and for generating latch-disabling signals at other latch-control ports,
- a data/instruction bus comprising a plurality of leads coupled in common between said controller bus ports and each of said peripheral components providing a path through which said data and instructions generated by said controller can be sent to said peripheral components, and
- a plurality of latches, each latch corresponding to one of said peripheral components and one of said latch-control ports and coupled between said peripheral component corresponding thereto and said bus, each latch including a latch-enable port, coupled to the latch-control port to which that latch corresponds, for forwarding data and instructions from the data/instruction bus to the peripheral component corresponding thereto in response to enabling signals at its enable port but not in response to disabling signals thereat.
A method of controlling a plurality of peripheral components of a telephone answering machine coupled to a controller through a common multi-lead bus, said controller generating data intended for said peripheral components, and for receiving instructions from inputting means comprising a plurality of buttons coupled in a matrix comprising columns and rows, each row of said matrix being coupled to a lead of said bus, each of said buttons in said matrix being coupled between one of said rows and one of said columns and operable to be placed in either an open circuited state or a closed circuit state, comprising the steps of:
- A) controlling said peripheral components by:
- i) placing data intended for at least one of said peripheral components on said bus,
- ii) enabling at least one of said peripheral components to receive said data, and
- iii) disabling all other of said peripheral components from receiving said data, and
- B) receiving instructions from the inputting means by:
- i) disabling all of said peripheral components from receiving said data, and
- ii) observing said inputting means to determine its condition by:
- a) biasing said columns of buttons with a preselected voltage to a first state,
- b) setting all but a selected one of said bus leads to said first state,
- c) setting said selected one bus lead to a second state, a column containing a closed-circuited button in the row corresponding to said selected bus lead is set to said second state while all other columns are set to said first state, and
- d) observing said columns to determine which of said buttons are closed circuited.
A telephone answering device comprising:
- A) a plurality of peripheral components including:
- i) a display control unit,
- ii) at least one indicator light, and
- iii) an audio control unit for directing audio signals in said telephone answering device,
- B) a microprocessor for generating data and instructions for controlling said peripheral components,
- C) a data/instruction bus comprising a plurality of leads coupled in common between said microprocessor and said peripheral components and providing a path through which said data and instructions generated by said microprocessor can be sent to said peripheral components,
- D) a plurality of latches, each latch corresponding to one of said peripheral components, said latch coupled between the peripheral component corresponding thereto and said bus,
- E) a plurality of latch control ports on said microprocessor, each latch control port corresponding to one of said latches and coupled to an enable input of the latch to which that latch control port corresponds,
- F) means in said microprocessor for placing said data and instructions on said bus, and
- G) means in said microprocessor for selectively placing an ENABLE LATCH signal on one of said latch enable ports corresponding to one of said peripheral components for which data or instructions placed on said bus are intended, said ENABLE LATCH signal enabling the corresponding latch whereas all other latches are not enabled.
Dependencies are inferred from the claim text.