Mechanism to accelerate counter testing without loss of fault coverage

Abstract

Test circuitry for a counter of n number of bits is described. The circuitry includes that which divides the counter into s number of segments when the counter is being tested in a test mode. The invention also includes circuitry for detecting when each segment nears the last count and overriding test mode to reenable a between-segment clock path between the segments before the last count to permit the last count to ripple through the counter to test connections between the segments on the next clock cycle. Previous test implementations did not test the interface between segments because of the prohibitive cost in tester time. In one embodiment, assuming equal numbers of b bits per segment, to fully test a counter using previous techniques, 2.sup.(n-b) +2.sup.b clock cycles would be required. In this technique, only (s-2)+2.sup.b clock cycles are required.

Dependencies are inferred from the claim text.