A frequency-shift keying (FSK) receiver of double superheterodyne type for receiving an FSK modulated wave having a radio frequency, said FSK modulated wave being obtained by frequency modulating a carrier wave by a baseband signal indicative of a binary digital signal, said FSK receiver comprising:
- a phase-locked loop (PLL) local oscillator for ensuring a phase-locked loop for said FSK modulated wave to produce a first local oscillation signal which is necessary for demodulation of said FSK modulated wave, said first local oscillation signal having a first local frequency which is variable;
- said PLL local oscillator comprising a voltage controlled oscillator (VCO) supplied with a control voltage signal for generating a voltage controlled signal as said first local oscillation signal, a PLL circuit connected to said voltage controlled oscillator for producing a phase difference signal in response to said voltage controlled signal, and a loop filter connected to said PLL circuit and said voltage controlled oscillator for filtering said phase difference signal to said control voltage signal;
- demodulating means supplied with said FSK modulated wave and connected to said PLL local oscillator for demodulating said FSK modulated wave into a demodulated signal using said first local oscillation signal and a second local oscillation signal having a second local frequency which is fixed, said demodulated signal being a replica of said baseband signal, said demodulating means reproducing said binary digital signal obtained by deciding said demodulated signal;
- control signal producing means connected to said demodulating means for producing a control signal when said demodulated signal has a mean value indicative of a deviation from a phase lock in said phase-locked loop;
- synchronizing means connected to said demodulating means for establishing bit and frame synchronization according to said binary digital signal to produce a synchronization detection signal when said bit and frame synchronization is established;
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- intermittent driving means connected to said PLL local oscillator, said control signal producing means, and said synchronizing means for making said PLL local oscillator intermittently operate according to said control signal and said synchronization detection signal, said intermittent driving means making said PLL local oscillator to stop its PLL operation when said control signal is absent, said intermittent driving means making said PLL local oscillator to activate said PLL operation when said control signal is present, said intermittent driving means supplying a VCO on/off signal to said voltage controlled oscillator to make said voltage controlled oscillator turn on/off, said intermittent driving means supplying a PLL on/off signal to said PLL circuit to make said PLL circuit turn on/off, said PLL on/off signal indicating ON for a time interval sufficient so that said voltage controlled oscillator is put into a normal oscillation state, said VCO on/off signal indicating ON for a time duration which is longer than said time interval, whereby said voltage controlled oscillator free runs although said PLL circuit is turned off.