Synchronous data interface circuit and method of equalizing synchronous digital data therefor

A synchronous data interface circuit which receives digital data, wherein the digital data comprises a synchronous non-return to zero (NRZ) data signal, a bit clock signal and a frame synchronizing signal, wherein the synchronous NRZ data signal is received through a first line, the bit clock signal is received through a second line, and the frame synchronizing signal is received through a third line, and wherein the first line, the second line and the third line are of a same length and are made of a same material, the synchronous data interface circuit comprising:

• an amplitude detector for detecting the amplitude of the bit clock signal received through the second line, the amplitude detector comparing the detected amplitude with a predetermined value and outputting a signal indicative thereof;
• and
• three equalizers, respectively, connected to each of the first, second and third lines, the equalizers further being connected to the amplitude detector, the equalizers compensating amplitude distortions of the synchronous NRZ data signal received through the first line, the bit clock signal received through the second line, and the frame synchronizing signal received through the third line in accordance with the signal received from the amplitude detector.