Device and method for measuring the jitter of a recovered clock signal
AssigneeNational Semiconductor Corporation
InventorHee Wong
Life of this patent
Estimating the term…
Abstract
A jitter extraction circuit, which includes a cyclic phase differentiator, a control loop, and a jitter integrator, measures the jitter of a recovered clock signal formed from an incoming data bit stream. The phase differentiator differentiates a phase data word, which includes both a jitter component and a delta frequency component, to produce a differentiated phase data word. The control loop estimates and removes the delta frequency component to produce a filtered data word which primarily represents the jitter component. The jitter integrator recovers the original jitter component by integrating the filtered data word to produce a jitter data word. The jitter of the recovered clock signal is determined by the statistics of the jitter data words.
Claims16
A jitter extraction circuit for measuring the jitter of a recovered clock signal, the jitter extraction circuit comprising:
- a cyclic phase differentiator that receives a plurality of successive r-bit phase data words containing phase movement information of the recovered clock signal, and that differentiates the phase data words to produce a plurality of successive two-bit differentiated phase data words, r representing an integer greater than four;
- a control loop that estimates and removes a delta frequency component from the plurality of differentiated phase data words to produce a plurality of successive t-bit filtered data words, where t represents an integer greater than two, each filtered data word having a value;
- and
- a jitter integrator that integrates the t-bit filtered data words to produce a plurality of successive jitter data words, the jitter data words having a value.
A jitter extraction circuit for measuring the jitter of a recovered clock signal, the jitter extraction circuit comprising:
- a cyclic phase differentiator that receives a plurality of successive r-bit phase data words containing phase movement information of the recovered clock signal, where r represents an integer, and that differentiates the phase data words to produce a plurality of successive s-bit differentiated phase data words, where s represents an integer less than r;
- a velocity subtracter that receives a plurality of successive m-bit estimated delta frequency data words and the plurality of differentiated phase data words so that each estimated delta frequency data word has a corresponding differentiated phase data word, and that produces a plurality of successive t-bit filtered data words in response thereto, each filtered data word being produced by subtracting each estimated delta frequency data word from the corresponding differentiated phase data word;
- a velocity integrator that receives the plurality of t-bit filtered data words, and that integrates the filtered data words to produce a plurality of successive z-bit integrated delta frequency data words;
- a pulse density modulation circuit connected between the velocity integrator and the velocity subtracter that produces one of the m-bit filtered data words each time a value represented by the integrated delta frequency data word is greater than an upper value or less than a lower value;
- and
- a jitter integrator that integrates the t-bit filtered data words to produce a plurality of successive jitter data words.
A jitter extraction circuit for measuring the jitter of a recovered clock signal, the jitter extraction circuit comprising:
- a cyclic phase differentiator that receives a plurality of successive r-bit phase data words containing phase movement information of the recovered clock signal, where r represents an integer, and that differentiates the phase data words to produce a plurality of successive s-bit differentiated phase data words, where s represents an integer less than r;
- a velocity subtracter that receives a plurality of successive m-bit estimated delta frequency data words and the plurality of differentiated phase data words so that each estimated delta frequency data word has a corresponding differentiated phase data word, and that produces a plurality of successive n-bit subtracted phase data words, where n represents an integer greater than s, in response thereto, each subtracted phase data word having a value and being formed by subtracting each estimated delta frequency data word from the corresponding differentiated phase data word;
- a redistribution circuit that produces a plurality of successive t-bit filtered data words, where t represents an integer less than n, by redistributing the values of the filtered data words to values that represent the values of the plurality of subtracted data words over time;
- a velocity integrator that receives the plurality of t-bit filtered data words, and that integrates the filtered data words to produce the plurality of m-bit estimated delta frequency data words;
- and
- a jitter integrator that integrates the t-bit filtered data words to produce a plurality of successive jitter data words.
A method for measuring the jitter of a recovered clock signal, the method comprising the steps of:
- obtaining a phase difference between a reference clock signal and an incoming data bit stream;
- generating a plurality of successive r-bit phase data words in response to the phase difference, each phase data word containing phase movement information of the recovered clock signal;
- differentiating the phase data words to produce a plurality of successive two-bit differentiated phase data words, where r represents an integer greater than four;
- estimating and removing a delta frequency component from the differentiated phase data words to produce a plurality of successive t-bit filtered data words, where t represents an integer;
- and
- integrating the filtered data words to produce a plurality of successive jitter data words.
A jitter extraction circuit for measuring the jitter of a recovered clock signal, the jitter extraction circuit comprising:
- a cyclic phase differentiator that receives a plurality of successive r-bit phase data words containing phase movement information of the recovered clock signal, and that differentiates the phase data words to produce a plurality of successive s-bit differentiated phase data words, r and s representing integers where r is more than two times greater than s;
- a control loop that estimates and removes a delta frequency component from the plurality of differentiated phase data words to produce a plurality of successive t-bit filtered data words, where t represents an integer greater than s;
- and
- a jitter integrator that integrates the t-bit filtered data words to produce a plurality of successive jitter data words.
Dependencies are inferred from the claim text.