Parity inversion test system

A parity inversion test system comprising:

• interface means having an input side coupled to a N-bit data line and an output side coupled to a M-bit data line, where N<M;
• input coupling means, coupled to the N-bit data line and to the input side of said interface means, said input coupling means receiving a signal indicative of a normal mode and a signal indicative of a test mode and providing a data input to the input side of said interface means and coupling at least a part of said data input to the input side of said interface means to the data input to said interface means in response to said signal indicative of a test mode so as to input a M-bit data to said interface means;
• parity generating means, coupled to the M-bit data line, for generating a parity data with respect to the M-bit data output to the M-bit data line from said interface means based on the M-bit data output from said interface means;
• and
• parity inversion bit specifying means, coupled to said parity generating means, for specifying arbitrary bits of the M-bit data output to said M-bit data line which are to be inverted when generating the parity data in said parity generating means.