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AssigneeAlcatel
InventorWerner J. C. Stessens
Estimating the term…
The error detection and correction device detects and corrects single bit errors in a sequence of bits comprising a plurality of n-bit containing subsets applied on a parallel bus IN having m subset parts. It includes a storage module ST connected to the bus IN and which transfers the subsets as they are received on the bus to a divider logic circuit DL. This circuit performs a m*n bit parallel modulo 2 division of the received sequence by a given polynomial and transfers the remainder REM to a comparison circuit C where it is compared with a zero byte or with an error code byte HEC contained in the sequence depending on the position of the first byte of the sequence on the bus. Based on the result of the comparison and using translation tables a processor circuit PR determines the bit position in the sequence of a bit error. A correction logic CL corrects the received sequence.
Error detection and correction device for detecting and correcting possible erroneous bits in a sequence of bits by performing an error detection algorithm on said sequence, wherein said sequence comprises a plurality of n-bit containing subsets applied to a parallel bus having m subset parts and that said error detection and correction device includes a detection means (DM) to detect to which one of said subset parts a first and a last subset of said sequence is applied, and a processing means (PM) to perform said algorithm in steps on sets of m subsets taken from the subsequent subsets of said plurality preceded by p-1 zero subsets and followed by m-q zero subsets if said first subset is applied to a p th one of said subset parts and if said last subset of said sequence is applied to a qth one of said subset parts, p and q being integers greater than zero and not exceeding m.
Dependencies are inferred from the claim text.