Circuit tester with coincident sequencing of independently compressed test data matrix segments

An electronic circuit tester comprising:

• a plurality of conductors for providing an electrical connection to an electronic device to be tested;
• a plurality of vector storage units, each unit storing one or more test vector signals, each signal corresponding to at least a portion of a test vector;
• a plurality of driver/comparator means for applying an electrical signal to one of said conductors in response to a test vector signal received from one of said vector storage means and receiving an electrical signal on one of said conductors and comparing it to a test vector signal received from one of said vector storage units;
• and
• a plurality of sequencer means, each of said plurality of sequencer means for storing an independently compressed segment of test data and causing one or more of said vector storage units to output said one or more test vector signals, wherein each sequencer means controls less than all of said plurality of conductors of said device to be tested;
• and
• clock means for applying a timing signal to each of said sequencer means;
• and
• wherein each of said sequencer means operates independently of the other of said sequencer means, except for said timing signal, and the test data stored in each of said sequencer means is independent of the test data stored in the other of said sequencer means.

A method of testing an electronic circuit comprising the steps of:

• providing a complete test matrix;
• dividing said complete test matrix into matrix segments;
• independently compressing each matrix segment to a set of unique vector segments;
• storing each set of unique vector segments in one or more vector storage units;
• and
• simultaneously sequencing each set of stored unique vector segments to reproduce said complete test matrix.