Phase locking circuit for jitter reduction in a digital multiplex system

#The present invention relates to a phase locking circuit for jitter reduction in a digital multiplex system and for control of the transmission of data bits from a buffer store, including a feed-back operational amplifier.

#In a digital multiplexer of the digital cross connect (DXC) type, there is required to perform conversions of digital bitstreams from one frequency to another. A bitstream may have a certain physical transmission rate and still perform a data transfer at a lower, effective rate, by inserting bits not containing any information in the data stream. The physical frequency of the incoming bitstream could in many cases be assumed to vary very little but instead the effective data frequency will often vary more, i.e., there is a very small physical jitter and a larger effective digital jitter inherent in the data stream. The frequency of the converted bitstream should naturally be as constant as possible but it can be allowed to have a small variation within the actual standards of acceptable jitter level. Of course, this could be handled by continuously storing very wide segments of the incoming data in a large buffer store and then transmit the stored data at the frequency required. This will necessarily be time-consuming and cause a considerable delay in the transfer of data and also be costly due to the large buffer store. A smaller buffer store can instead be used if it is provided with some efficient control means for the forwarding of data bits from the buffer. This control means may comprise a phase locked circuit or loop (PLL) and it shall lock on to frequency differences, which requires "large" gain and "large" bandwidth. When the system has been phase locked, the output data stream forwarded from the buffer shall thus have a low inherent jitter, which requires "low" gain due to digitally generated jitter in the multiplex system.

#Solutions up to now have comprised the manipulation of gain and bandwidth, with accompanying problems, either with jitter or locking. In U.S. Pat. No. 4,952,887 to Ashley a phase-lock loop circuit is disclosed, which is said to have improved acquisition time and stability with respect to varying input signal strengths. The loop filter circuit comprises two diodes coupled in anti-parallel to one input of an operational amplifier. The circuit is intended to be used in an analog divider.

#An embodiment of the circuit according to the invention, given as an illustrative example, will now be described in more detail with reference to the accompanying drawings on which:

#FIG. 1 illustrates a block diagram of a device for the conversion of a digital data stream to a lower frequency;

#FIG. 2 illustrates the construction of a FIFO-buffer used in the device in FIG. 1; and

#In FIG. 1 a circuit is illustrated allowing an incoming data stream to be forwarded at a lower frequency. At the input line 1 thus line coded data enters at 184,32 Mbit/s. This pulse stream is fed to an interface 3 where the pulses are given a suitable voltage level and a proper shape and forwarded on an output line 5 from the interface 3. Also a clock pulse stream is extracted from the incoming line coded data and is forwarded from the interface 3 on a line 7 in the shape of a regular square wave having the same frequency as the incoming pulse train on line 1. These two signals output from the interface 3 are fed to a device 9 for frame-locking and removal of extra superfluous bits from the data stream. In the device 9 the incoming bit stream is analyzed for establishing the frames on which the proper information is sent in said stream and thus for deciding which bits shall be removed from the data stream. The bit removal device outputs on a line 11 a reduced clock bit pulse train which coincides with the constructed clock pulses on line 7 except that some of the pulses have been removed. The average number of clock pulses will correspond to the desired output frequency from the whole circuit depicted in FIG. 1.

#In FIG. 2, a central unit in this circuit is a buffer, buffer store or FIFO-register 13 having a limited size, for instance as indicated allowing 160 data bits to be stored therein. The FIFO-register 13 receives the shaped pulse signal from line 5 and the reduced clock bit pulse train on line 11 from the bit removal device 99. In the FIFO-register 13 the data bits incoming from line 5 are clocked into the register and stored therein controlled by the clock bits on line 11. Thus only data bits corresponding to the pulses on line 11 are actually stored in the register 13. This will mean that possible pulses corresponding to absent pulses in the reduced clock bit pulse train on line 11 are discarded.

#The FIFO-register 13 outputs on a line 15 the stored data bits sequentially and this data pulse train having a lower frequency arrives to an output interface 17, which will shape the pulses of the incoming pulse train and give them a suitable voltage level to be forwarded from the entire circuit of FIG. 1 on the output line 19, e.g., as indicated in the figure at a nominal frequency of 139,264 Mbit/s.