US 5,402,417 AGranted

Packet switching system

AssigneeNEC Corporation

InventorToshiya Aramaki

Life of this patent

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Abstract

A packet switching system includes a plurality of incoming channels, through which packets arrive. The system has a circuit providing arrival time information for header information of respective packets. The arrival time information is then copied by a copying circuit. The copied information is accumulated in an arrival time information accumulating circuit in an order of the arrival time. On the other hand, the packet is accumulated by a packet accumulating circuit in an order of the arrival time. A control circuit is adapted to output the packets accumulated in the packet accumulating circuit and having the arrival time information consistent with the arrival time information accumulated at the leading end of the arrival time information accumulating circuit. The packets are output from the packet accumulating circuit according to destinations contained in the header information thereof through a plurality of outgoing channels for feeding out the routed packets.

Claims7

Dependent claims

A packet switching system, comprising:

a plurality of incoming channels, through which packets arrive;
time information providing means for providing arrival time information in header information of respective packets;
time information detecting means for detecting said arrival time information provided in the header information of respective packets;
time information buffer means for accumulating the detected arrival time information in the order of the arrival time;
packet sorting buffer means for accumulating said packets provided with the arrival time information in the header information in the order of arrival thereto;
control means for outputting the packets accumulated in said packet sorting buffer means and having the arrival time information consistent with the arrival time information accumulated at a leading end of said time information buffer means;
first switching means for routing the packets output from said packet sorting buffer means according to a destination contained in the header information thereof;
and
a plurality of outgoing channels for feeding out the routed packets.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/198,266Filed 18 Feb 1994
Priority: JP 5-03366323 Feb 1993
Granted: 28 Mar 1995
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H04Q 11/0478
Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral,…:…
H04L 49/1507
Interconnection of switching modules: distribute and route fabrics, e.g. sorting-routing or Batcher-Banyan
H04L 49/3018
Peripheral units, e.g. input or output ports: input queuing
H04L 49/3027
Peripheral units, e.g. input or output ports: output queuing