Fuse selectable timing signals for internal signal generators
AssigneeTexas Instruments Incorporated
InventorsDuc Ho, Duy-Loan T. Le, Kenneth A. Poteet, Scott E. Smith
Life of this patent
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Abstract
Switching circuits controlled by a fuse that can be blown after testing the DRAM part select the timing signals coupled from a binary counter to internal signal generator circuits. The internal Circuits control self refresh in this embodiment. The decision to leave the fuse intact or blow the fuse rests on the test results obtained from each part and can vary depending upon maturity of the manufacturing process, the pause test results obtained and whether a low power part is desired. The fuse is affected after fabrication of the chip and at the same time as other fuses used for redundancy. This provides another degree of freedom in the manufacture of integrated circuits.
Claims18
A dynamic random access memory part comprising:
- an array of memory cells for storing one data bit in one data cell, the array of memory cells including redundant cells selected by fuses after testing of the part to replace defective memory cells;
- peripheral circuits for generating internal signals to operate the array of memory cells upon receipt of timing signals representing selected times;
- oscillator circuits for producing a clock signal, the clock signal occurring at a frequency that can vary from part to part;
- timing circuits receiving the clock signal and producing the timing signals;
- switch circuits coupling selected timing signals between the timing circuits and the peripheral circuits in response to receipt of a switch signal;
- and
- fuse circuits including a fuse and producing said switch signal in response to the fuse being open and closed.
Switching circuits for a dynamic random access memory part that includes true and inverted binary count signals used for timing, the switching circuits comprising:
- pass circuits having a pair of inputs, which receive the true and inverted states of the same binary count, an output and two pairs of transistors, each pair of transistors being connected to one of the inputs, each pair of transistors including an N-channel transistor and a P-channel transistor connected in parallel, the gate of the N-channel transistor in one pair being connected to the gate of the P-channel transistor in the other pair, both pairs of transistors being connected to the output, the pass circuits including an inverter having an input connected to the gate of one N-channel transistor and having an output connected to the gate of the other N-channel transistor;
- and
- fuse circuits including a fuse and a latch, the fuse being connected in series between a pair of transistors and to the input to the latch, the output of the latch being connected to the input of the inverter in the pass circuits.
A process of making a dynamic random access memory part comprising:
- fabricating the part to include fuses for selecting redundant cells that replace defective cells and to include at least one fuse for selecting between certain timing circuits signals;
- testing the part to ascertain the location of defective cells and ascertain the frequency of timing circuits;
- affecting the fuses to select redundant cells for replacing the defective cells;
- and
- affecting the at least one fuse to select between the certain timing circuits signals.
A dynamic random access memory part comprising:
- an array of memory cells;
- peripheral circuits for generating internal signals to operate the array of memory cells in response to timing signals;
- and
- timing circuits for generating the timing signals, the timing circuits including a fuse, the fuse capable of being blown after fabrication of the part, wherein blowing of the fuse changes the timing circuits wherein at least one timing signal is altered by a predetermined amount.
A process for fabricating a dynamic random access memory part, the process comprising the steps of:
- in a part in which timing signals are used to control operation of an array of storage cells, fabricating the a timing circuit in the part to include a fuse, wherein a state of the fuse determines a timing property of at least one timing signal, a state of the fuse capable of being changed after fabrication of the part.
Dependencies are inferred from the claim text.