Synchronous memory having parallel output data paths

A synchronous static random access memory, comprising:

• a plurality of memory cells, each memory cell coupled to a bit line and to a word line;
• a column decoding circuit, coupled to the bit lines, for providing a data signal corresponding to data stored in a selected memory cell during a read cycle of the memory;
• a first register, having an input terminal coupled to the column decoding circuit, and an output terminal, the first register for receiving a data signal from the column decoding circuit in response to a first clock signal being in a first logic state;
• a second register, having an input terminal coupled to the column decoding circuit, and an output terminal, the second register for receiving the data signal from the column decoding circuit in response to a second clock signal being in the first logic state;
• and
• an amplifier circuit, having a first input terminal coupled to the output terminal of the first register, a second input terminal coupled to the output terminal of the second register, a control terminal for receiving a second clock signal, and an output terminal, the amplifier alternately receiving the data signals from the first and second registers in response to the second clock signal.

A synchronous integrated circuit memory, comprising:

• a plurality of memory cells, each memory cell coupled to a bit line and to a word line;
• and
• at least two parallel output data registers, coupled to the plurality of memory cells, the parallel output data registers for providing at least two parallel data paths, the parallel data paths being made alternately conductive in response to a clock signal;
• wherein the parallel data paths for providing an increased time in which a data signal is valid during a read cycle of the memory.