Word line decoder/driver circuit and method

A driver circuit on a semiconductor memory, comprising:

• an input node coupled to receive a row select signal,
• a driver stage for amplifying the row select signal;
• a switching clamp, coupled to the driver stage, for reducing the effects of overshoot in the driver stage;
• an output node for outputting the amplified row select signal;
• and
• a row coupled to the output node and being selected in response to the amplified row select signal.

A circuit on a semiconductor memory, comprising:

• a translating stage for receiving a deselect signal at a first voltage and translating it to a second voltage;
• a row;
• a driver stage coupled between the translating stage and the row, wherein the driver stage has a voltage drop approximately equal to the second voltage and;
• a current mirror coupled to the driver stage.

A method of driving a selected row in a memory array, comprising the steps of:

• receiving a signal at an input node of an amplifying stage;
• amplifying, in a series of cascaded amplifier stages, the row select signal;
• pulling up an output node, coupled to a selected row in a memory array, in response to the amplified row select signal;
• and
• in the event of voltage overshoot conditions in the cascaded amplifier stages, turning on a clamp to shunt excess current away from the cascaded amplifier stages.

A method of reducing power consumption of a deselected row in a memory array, comprising the steps of:

• receiving a row deselect signal at a first predetermined voltage;
• translating the row deselect signal to a second predetermined voltage;
• applying the translated row select signal at the second predetermined voltage at an input node of a driver circuit having a voltage drop approximately equal to the second predetermined voltage;
• outputting the row deselect signal at an output node of the driver circuit and;
• providing a current mirror to substantially minimize any current from being dissipated at the output node.

A row driver circuit on a semiconductor memory, comprising:

• an input node for receiving either a row select or a row deselect signal;
• a translator for translating the row select signal or the row deselect signal;
• an amplifier stage for amplifying the translated row select signal, or reducing the potential of the row deselect signal for minimizing power dissipation of the amplifier stage in response to the row deselect signal;
• a clamp, coupled to the amplifier stage, for reducing the effect of overshoot in the amplifier stage in response to the row select signal;
• a row coupled to the output of the amplifier stage and selected in response to the row select signal or deselected in response to the row deselect signal.