Dynamic ram
AssigneeCitizen Watch Co., Ltd.
InventorKenzo Fujisawa
Life of this patent
Estimating the term…
Abstract
A refresh switching circuit for a dynamic RAM which is capable of easily switching a RAS-only refresh to a CAS-before-RAS refresh, thereby consuming less electric power, easily executing a shift to a self-refresh (suspending), and obtaining comparability with conventional personal computer systems. The dynamic RAM comprises a CPU (101), dynamic RAM arrays (115) and a system logic (110) for use in a microprocessor system, and further comprises a refresh switching circuit (111) for switching the RAS-only refresh to the CAS-before-RAS refresh.
Claims20
A dynamic RAM in a microprocessor system including a central processing unit, a dynamic RAM array and a system logic, said dynamic RAM comprising a refresh switching circuit having means for converting RAS-only refresh to CAS-before-RAS refresh in response to RAS and CAS signals when the RAS-only refresh is executed for the dynamic RAM array.
A refresh switching circuit for a microprocessor system having a central processing unit, a system logic, and a dynamic RAM array, said circuit having means for converting a RAS-only refresh command from said system to a CAS-before-RAS refresh, thereby reducing power consumed by said system during a refresh operation.
A method for refresh switching in a microprocessor system, said system having a central processing unit, a system logic, a dynamic RAM array, and a refresh switching circuit, the method comprising the steps of:
- inputting a RAS signal to said switching circuit;
- and converting said RAS signal to CAS-before-RAS refresh signals when said system is in a refresh operation.
Dependencies are inferred from the claim text.