Circuit for generating a clock signal to separate bit lines in a semiconductor memory device

A semiconductor memory device, comprising:

• a first memory cell array;
• a second memory cell array separated from said first memory cell array;
• a first bit line pair for accessing selected memory cells of said first memory cell array with data exhibiting first logic states at a first voltage;
• a second bit line pair for accessing selected memory cells of said second memory cell array with data exhibiting said first logic states at said first voltage;
• an equalizing circuit for equalizing potential differences between bit lines comprising said first bit line pair and for equalizing potential differences between bit lines comprising said second bit line pair;
• a first separation gate exhibiting a threshold voltage, and connecting said first bit line pair to a first sense amplifier in response to a first clock signal;
• a second separation gate exhibiting said threshold voltage, and connecting said second bit line pair to a second sense amplifier in response to a second clock signal;
• and
• supply means coupled to receive a second voltage exhibiting an amplitude differing from said first voltage by not less than said threshold voltage, for selectively providing said first clock signal with an amplitude equal to said second voltage to said first separation gate for enabling said first bit line pair to access the selected memory cells of said first memory cell array, and for providing said second clock signal with an amplitude equal to said second voltage to said second separation gate for enabling said second bit line pair to access the selected memory cells of said second memory cell array, in dependence upon a block select signal.

A semiconductor memory device, comprising:

• a memory cell array comprising a plurality of memory cells;
• a plurality of bit line pairs conducting data exhibiting a first logic state having a first amplitude;
• equalizing means for equalizing potential differences between the bit line pairs;
• sense amplifying means for sensing data conducted by said bit line pairs;
• isolation means exhibiting a threshold voltage drop, for selectively isolating said bit line pairs from said sense amplifying means in dependence upon isolation signals;
• and
• means for providing, in response to an address signal, said isolation means with the isolation signals at a first voltage having a second amplitude differing from said first amplitude by not less than said threshold voltage, and for providing said equalizing means with a second voltage having said first amplitude, said providing means comprising:
• driver means for generating an intermediate signal having said second amplitude in response to address signals;
• first and second inverters each coupled to receive said intermediate signal, for providing first and second inverted signals;
• and
• a first serially connected pair of transistors disposed between a high voltage terminal and a reference voltage terminal, for receiving said first and second inverted signals, respectively, and for providing said isolation signals at said first voltage having said second amplitude to said isolation means for enabling the bit line pairs to transfer said data into selected memory cells of said memory cell array;
• third and fourth inverters each coupled to receive said intermediate signal, for providing third and fourth inverted signal;
• and
• a second serially connected pair of transistors disposed between said high voltage terminal and said reference voltage terminal, for receiving said third and fourth inverted signals, respectively, and for providing said second voltage having said first amplitude to said equalizing means for equalizing the potential differences between the bit line pairs.

A semiconductor memory device, comprising:

• a first memory cell array;
• a first bit line pair for accessing said first memory cell array with data having a first a first logic state having a first amplitude;
• first separation gate means exhibiting a threshold voltage, for connecting said first bit line pair to said first memory cell array in response to a first separation clock signal;
• and
• first clock driver means coupled to receive a first voltage having a second amplitude differing in value from said first amplitude by not less than said threshold voltage, for generating said first separation dock signal at said second amplitude, said first clock driver means comprising:
• driver means for generating an intermediate signal having said second amplitude in response to address signals;
• first and second inverters each coupled to receive said intermediate signal, for providing first and second inverted signals;
• and
• a serially connected pair of first and second transistors disposed between a high voltage terminal and a reference voltage terminal, for receiving said first and second inverted signals, respectively, and for providing said first separation clock signal at said first voltage having said second amplitude to said first separation gate means for enabling the first bit line pair to transfer said data exhibiting said first logic state having said first amplitude into selected memory cells of said first memory cell array.

A semiconductor memory device, comprising:

• a first memory cell array;
• a second memory cell array;
• a first bit line pair for accessing said first memory cell array with data having a first logic state at a first voltage;
• a second bit line pair for accessing said second memory cell array with data having said first logic state at said first voltage;
• first sense amplifier means for amplifying and providing the data on said first bit line pair;
• second sense amplifier means for amplifying and providing the data on said second bit line pair;
• first separation gate means exhibiting a threshold voltage, for connecting said first bit line pair to said first sense amplifier means in response to a first separation clock signal;
• second separation gate means exhibiting said threshold voltage, for connecting said second bit line pair to said second sense amplifier means in response to a second separation clock signal;
• and
• bit line separation clock driver means coupled to receive a second voltage differing in amplitude from said first voltage by said threshold voltage, for generating said first separation clock signal at said second voltage to said first separation gate means for enabling said first bit line pair to access selected memory cells of said first memory cell array, and said second separation clock signal at said second voltage to said second separation gate means for enabling said second bit line pair to access selected memory cells of said second memory cell array;
• and
• an input/output gate coupled between said first sense amplifier means and said second amplifier means.