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AssigneesHitachi, Ltd., Hitachi Device Engineering Co., Ltd.
InventorsKenichi Ohhata, Hiroaki Nambu, Kazuo Kanetani, Youji Idei, Takeshi Kusunoki, Toru Masuda
Estimating the term…
A semiconductor memory device has a primary memory cell array, a primary decoder having a first circuit producing an intermediate signal from an address signal and a second circuit producing a first cell selection signal from the intermediate signal for selectively driving a word line and a bit line, an auxiliary memory cell array having a plurality of memory cells, each being used for a defective memory cell found in the primary memory cell array, an auxiliary decoder connected to the primary decoder to receive the intermediate signal, a non-volatile memory for storing first information indicating that the primary memory cell array contains a defective memory cell from which a cell defect signal is produced and for storing second information indicating an address of the defective memory cell from which a defective cell address signal is produced, and a control circuit responsive to the cell defect signal and the defective cell address signal for producing a first control signal to be supplied to the second circuit and a second control signal to be supplied to the auxiliary decoder. The primary decoder is prohibited by the first control signal from accessing a defective memory cell having an address represented by the defective cell address signal. The auxiliary decoder produces a second cell selection signal from the intermediate signal under control of the second control signal and of the cell defect signal for selectively accessing a memory cell in the auxiliary memory cell array.
A semiconductor memory device comprising:
Dependencies are inferred from the claim text.