Semiconductor memory having redundancy circuit

A semiconductor memory comprising:

• a plurality of memory blocks including normal memory blocks and spare memory blocks, each memory block including a plurality of memory cells;
• addressing means for generating address signals for selecting said normal memory blocks;
• a ROM for storing the address of a defective memory block of said normal memory blocks;
• comparing means for comparing the output of said ROM with said address signals;
• a plurality of sense circuits for sensing signals appearing on data lines coupled with said memory cells;
• a plurality of first switch means associated with said plurality of sense circuits each permitting or inhibiting a first DC voltage supply to each of said plurality of sense circuits according to the output of said ROM;
• and
• a plurality of second switch means associated with said plurality of sense circuits each permitting or inhibiting a control signal supply to each of said plurality of sense circuits according to the output of said ROM,
• wherein at least one of said control signals supplied from said plurality of second switch means activates the associated sense circuit.