Voltage converter arrangement for a semiconductor memory

A semiconductor memory comprising:

• a memory cell having a first MOS transistor;
• a data line coupled to a drain or a source of said first MOS transistor;
• a word line coupled to a gate of said first MOS transistor;
• and
• a voltage converter for converting an external supply voltage which is supplied from outside of said semiconductor memory, into an internal supply voltage which is supplied to said word line in said semiconductor memory;
• wherein said voltage converter comprises:
• a first circuit for supplying a first reference voltage of substantially constant magnitude irrespective of fluctuations of said external supply voltage;
• a second circuit for supplying a second reference voltage being dependent on magnitude of said external supply voltage, and independent from said first reference voltage;
• a second MOS transistor having a first source/drain terminal coupled to the external supply voltage;
• a first differential amplifier having an inverting input, a non-inverting input and an output, wherein the output is coupled to a gate of said second MOS transistor;
• a third MOS transistor having a first source/drain terminal coupled to the external supply voltage;
• a second differential amplifier having an inverting input, a non-inverting input and an output, wherein the output is coupled to a gate of said third MOS transistor;
• and
• an output terminal coupled to a second source/drain terminal of said second MOS transistor and a second source/drain terminal of said third MOS transistor,
• wherein the inverting input of said first differential amplifier is coupled to the output of said first circuit,
• the inverting input of said second differential amplifier is coupled to the output of said second circuit, and
• wherein both the non-inverting input of said first differential amplifier and the non-inverting input of said second differential amplifier are coupled to said output terminal.