Non-volatile semiconductor memory device and memory circuit using the same

A non-volatile memory circuit comprising a plurality of transistors formed in a matrix in the column direction and the row direction on a semiconductor substrate of a first conductivity type,

• each of said transistors having a structure comprising
• a source and a drain of a second conductivity type opposite to said first conductivity type, which are formed spaced apart from each other by a predetermined distance on a surface layer of said semiconductor substrate,
• a tunnel insulation film interposed between said source and said drain having such a thickness that charges produced in a channel region so formed as to be able to pass therethrough by tunneling, which is formed spaced apart from said source by a predetermined offset distance on the channel region,
• a floating gate formed on said tunnel insulation film for storing the charges which passed through the tunnel insulation film by tunneling,
• a capacitor insulation film formed on said floating gate for trapping the charges stored in the floating gate so as not to escape,
• a control gate formed on said capacitor insulation film, to which a predetermined control voltage is applied,
• a sidewall gate formed above the remaining channel region on the side of the source region where said tunnel insulation film is not formed, and
• insulating means for insulating said sidewall gate from the channel region, the floating gate, the capacitor insulation film and the control gate,
• a common word line being connected to respective control gates of the plurality of transistors arranged in the column direction for each column,
• a common bit line being connected to respective drains of the plurality of transistors arranged in the row direction for each row,
• a common source line being connected to respective sources of all the transistors, and
• a common substrate line connected to all the transistors being provided below the transistors.