US 5,402,373 A · Electrically erasable programmable read-only memory with electric field decreasing controller

Abstract

A NAND cell type EEPROM has bit lines, each of which is associated with a NAND cell unit including a series array of four memory cell transistors. Each transistor is a MOSFET with a control gate and a floating gate for data storage. The memory cell transistors are connected at their control gates to word lines, respectively. One end of the NAND cell unit is connected through a first select transistor to a corresponding bit line; the other end thereof is connected via a second select transistor to a source voltage. The memory cell transistors and the select transistors are arranged in a well region formed in a substrate. In an erase mode, the bit line voltage, the substrate voltage and the well voltage are held at a high voltage, whereas the word lines are at zero volts. The gate potential of the select transistors is held at the high voltage, whereby the internal electric field of these select transistors is weakened to improve the dielectric breakdown characteristic thereof.

Claims15

Dependent claims

An electrically erasable non-volatile semiconductor memory device comprising:

(a) a semiconductive substrate;
(b) data transfer lines arranged on said substrate;
(c) program lines insulatively intersecting said data transfer lines on said substrate to define cross points therebetween;
(d) field effect transistors at said cross points as memory cell transistors, each of said transistors having a carrier storage section and a control gate which is connected to a corresponding one of said program lines,
said memory cell transistors being divided into a plurality of cell units each of which has one of one memory cell transistor and a plurality of memory cell transistors;
(e) a switching transistor having an insulated gate and being provided at a first end portion of each of said cell units to selectively connect each of said cell units to a corresponding one of said data transfer lines;
and
(f) controller means for causing said insulated gate to be at a specific voltage which has a same polarity as a polarity of a preselected voltage to be applied to said substrate during an erase operation in said cell units;
wherein said control means permits a selected one or ones of said program lines to be at said specific voltage during the erase operation, to prevent certain memory cell transistors which are associated with the selected program line from being erased.

6 more elements

An electrically erasable and programmable read only memory comprising:

(a) a semiconductive substrate of a first type conductivity;
(b) data transfer lines arranged on said substrate;
(c) program lines insulatively crossing said data transfer lines on said substrate to define crossing points therebetween;
(d) a plurality of cell units associated with said data transfer lines and said program lines, each of said cell units having a plurality of memory cell transistors arranged at said crossing points, each of said transistors having a carrier storage layer and a control gate at which a corresponding program line is connected to each transistor,
said plurality of memory cell transistors having a first end connected to a corresponding data transfer line, and a second end connected to a source voltage together with the other series circuits;
(e) a metal insulator semiconductor field effect transistor provided at said first end as a first select transistor;
(f) a metal insulator semiconductor field effect transistor provided at said second end as a second select transistor;
(g) erase means for performing an erase operation by applying said substrate with a first voltage of positive polarity, and applying designated ones of said program lines with a second voltage which is lower than said first voltage, to change a carrier amount at the carrier storage portions of said memory cell transistors;
and
(h) voltage control means for causing said first and second select transistors to be at a third voltage of positive polarity during the erase operation, and for decreasing an electric field in said select transistors;
and
(i) a well region in said substrate of a second type conductivity, said memory cell transistors and said first and second select transistors being arranged in said well region;
wherein said voltage control means applies said third voltage to a selected one of said program lines, to prevent the memory cell transistors associated therewith from being erased, while allowing the remaining memory cell transistors to be erased.

10 more elements

Dependencies are inferred from the claim text.

Electrically erasable programmable read-only memory with electric field decreasing controller

Life of this patent

Electrically erasable programmable read-only memory with electric field decreasing controller

Life of this patent

Abstract

Claims15