Circuitry and method for selecting a drain programming voltage for a nonvolatile memory

A method for setting a drain programming voltage of a nonvolatile memory, comprising the steps of:

• (a) setting a first value corresponding to a first voltage level of the drain programming voltage;
• (b) sending the first value to a drain programming voltage generation circuit of the nonvolatile memory such that the drain programming voltage generation circuit generates the drain programming voltage in accordance with the first value;
• (c) selecting a plurality of memory cells of the nonvolatile memory for programming by applying the drain programming voltage to the selected plurality of memory cells for a predetermined programming time;
• (d) measuring a threshold voltage of one of the selected memory cells after programming;
• (e) comparing the threshold voltage measured with a predetermined programmed threshold voltage for the nonvolatile memory;
• (f) if the voltage level of the threshold voltage measured is not within a predetermined range of the predetermined programmed threshold voltage, then changing the drain programming voltage by changing the first value and repeating steps (b) through (e);
• (g) if the voltage level of the threshold voltage measured is within the predetermined range of the predetermined programmed threshold voltage, then storing the first value in the nonvolatile memory to constantly control the drain programming voltage generation circuit to generate the drain programming voltage in accordance with the first value such that the nonvolatile memory is programmed to the predetermined programmed threshold voltage within the predetermined programming time.

A nonvolatile memory residing on a single substrate, comprising:

• (A) a memory array having at least a first memory transistor coupled to a bit line, wherein the first memory transistor includes a drain region coupled to the bit line, a source region, a control gate, and a floating gate, wherein the first memory transistor further includes an effective channel length:
• (B) a drain programming voltage generation circuit coupled to a programming voltage source and the bit line for providing a drain programming voltage to the drain region of the first memory transistor via the bit line during programming of the first memory transistor, wherein the drain programming voltage generation circuit further comprises
• (i) a voltage setting circuit for setting the voltage level of the drain programming voltage, wherein the voltage setting circuit further comprises a second memory, transistor that has an effective channel length substantially equal to that of the first memory, transistor of the memory, array such that the drain programming voltage generation circuit generates the drain programming voltage that also varies with respect to the effective channel length of the first memory transistor;
• (ii) a current mirror circuit coupled to the programming voltage source for providing a substantially constant first current;
• (iii) a source follower circuit coupled to (1) the programming voltage source, (2) the current mirror circuit, (3) the voltage setting circuit, and (4) an output of the drain programming voltage generation circuit for providing the first current to the voltage setting circuit and for charging and settling the output node of the drain programming voltage generation circuit to the drain programming voltage, wherein the source follower circuit acts as a positive feedback loop to help the output node to be quickly charged to the drain programming voltage.