System and method for synthesizing logic circuits with timing constraints

A method of improving the timing performance of an integrated circuit, the steps of the method comprising:

• receiving and storing in a computer memory a netlist denoting a list of components in said integrated circuit and a set of nodes interconnecting said components;
• each said component of said integrated circuit having at least one input port and at least one output port, said set of nodes including a set of circuit input nodes and circuit output nodes for said integrated circuit;
• assigning an initial capacitance value to each said node;
• computing a routing difficulty value, comprising a sum of routing difficulty values associated with each of said nodes in said integrated circuit;
• adjusting said capacitance values for said integrated circuit so as to reduce said computed routing difficulty value;
• altering said capacitance values of said nodes so as to meet timing constraints;
• and
• passing said netlist and adjusted capacitance values to a silicon compiler and automatically placing/routing a circuit having said components and interconnection nodes with capacitance values not exceeding said adjusted capacitance values.

A computer aided design system for improving the timing performance of an integrated circuit, comprising:

• first input means and storage means for receiving and storing in a computer memory a netlist denoting a list of components in said integrated circuit and a set of nodes interconnecting said components;
• each said component of said integrated circuit having at least one input port and at least one output port, said set of nodes including a set of circuit input nodes and circuit output nodes for said integrated circuit;
• second input means and storage means for receiving and storing in a computer memory a plurality of timing constraints, each of said timing constraints including a first node and a second node of said circuit and a maximum delay for a signal to propagate from said first node to said second node;
• means for determining capacitance values for individual nodes of said nodes of said circuit so as to meet said timing constraints;
• and
• means for passing said netlist and capacitance values to a silicon compiler for automatically placing/routing a circuit having said components and interconnection nodes with capacitance values not exceeding said capacitance values.

A computer aided design system for improving the timing performance of an integrated circuit, comprising:

• input means and storage means for receiving and storing in a computer memory a netlist denoting a list of components in a specified integrated circuit and a set of nodes interconnecting said components;
• each said component of said specified integrated circuit having at least one input port and at least one output port, said set of nodes including a set of circuit input nodes and circuit output nodes for said specified integrated circuit;
• initial value assignment means, coupled to said storage means, for assigning an initial capacitance value to each said node;
• layout difficulty function means for computing a routing difficulty value, comprising a sum of routing difficulty values associated with each of said nodes in said specified integrated circuit;
• means for adjusting said capacitance values for said specified integrated circuit so as to reduce said computed routing difficulty value;
• means for altering said capacitance values so as to meet timing constraints;
• and
• means for passing said netlist and adjusted capacitance values to a silicon compiler to automatically place/route a circuit having said components and interconnection nodes with capacitance values not exceeding said adjusted capacitance values.