Data separator and signal processing circuit with an adjustable window

A disk recording apparatus wherein a synchronized read signal is produced from an original read signal read out from a disk shaped record medium, comprising:

• phase synchronizing means, into which said original read signal is input, for generating a clock pulse in synchronism with said original read signal;
• synchronizing means, into which said original read signal and said clock pulse produced from said phase synchronizing means are input, for producing said synchronized read signal by employing a window which has been formed based upon said clock pulse;
• window error detecting means, into which the output from said synchronizing means is input, for judging whether an error of said synchronized read signal occurs or not;
• window adjusting means for adjusting the timing of said window and said original read signal according to the result of the window error detection;
• wherein said original read signal is inputted to said window adjusting means, and said window adjusting means includes a controllable variable delay means in a signal path to said synchronizing means for adjustably delaying said original read signal;
• means for shifting said delay means;
• means for obtaining a maximum and minimum delay amount through said shifting means from said output from said window error detecting means;
• means for dividing the maximum and minimum delay amount into an arbitrary ratio;
• and
• means for setting said delay means at said divided delay amount.

A disk recording apparatus wherein a synchronized read signal is produced from an original read signal read out from a disk shaped record medium, comprising:

• phase synchronizing means, into which said original read signal is input, for generating a clock pulse in synchronism with said original read signal;
• synchronizing means, into which said original read signal and said clock pulse produced from said phase synchronizing means are input, for producing said synchronized read signal by employing a window which has been formed based upon said clock pulse;
• window error detecting means, into which the output from said synchronizing means is input, for judging whether an error of said synchronized read signal occurs or not;
• and
• window adjusting means for adjusting the timing of said window and said original read signal according to the result of the window error detection;.
• wherein said original read signal is inputted to said window adjusting means, and said window adjusting means includes a controllable variable delay means in a signal path to said synchronizing means for adjustably delaying said original read signal;
• wherein said delay means equipped with a tap includes an arrangement in which a CMOS inverter gate is alternately series-connected to a Bipolar-CMOS inverter gate.

A signal processing circuit used in an apparatus for writing/reading data on/from a disk-shaped recording medium, comprising:

• phase synchronizing means, into which an original read signal from said recording medium is input, for generating a clock pulse in synchronism with said original read signal;
• synchronizing means, into which said original read signal and said clock pulse produced from said phase synchronizing means are input, for producing a synchronized read signal by employing a window which has been formed based upon said clock pulse;
• window error detecting means, into which the output from said synchronizing circuit is input, for judging whether an error has occurred in said synchronized read signal.;
• and
• window adjusting means for adjusting the timing of said window and said original read signal according to the result of the window error detection;
• wherein said original read signal is inputted to said window adjusting means, and said window adjusting means includes a controllable variable delay means in a signal path to said synchronizing means for adjustably delaying said original read signal;
• wherein said delay means equipped with a tap includes an arrangement in which a CMOS inverter gate is alternately series-connected to a Bipolar-CMOS inverter gate.

A method of producing a synchronizing signal from an original read signal read out from a disk shaped record medium, comprising the steps of:

• producing a clock pulse forming a window in synchronism with said original read signal;
• shifting gradually the timing of said window and said original read signal;
• detecting whether an error of said synchronizing signal occurs or not during said shifting;
• selecting a suitable shifting amount calculated from the result of the error detection according to a predetermined algorithm;
• producing said synchronizing signal with the window based on the shifting amount;
• and
• memorizing a maximum and a minimum shifting amount, at which said error is not detected, during said shifting step.

A disk recording apparatus wherein a second read signal is produced from a first read signal read out from a disk shaped record medium, comprising:

• phase synchronizing means, into which said first read signal is input, for generating a clock pulse in synchronism with said first read signal;
• synchronizing means, into which said first read signal and said clock pulse produced from said phase synchronizing means are input, for producing said second read signal by employing a window which has been formed based,upon said clock pulse;
• window error detecting means, into which the output from said synchronizing means is input, for judging whether an error of said second read signal has occurred or not;
• apparatus for reading out data from said window error detecting means which indicates whether an error of said second read signal has occurred or not and outputting control data which adjusts the timing of said window;
• window timing varying means for varying the relative timing of said window and said first read signal according to the data from said memory means;
• wherein said first read signal is inputted to said window timing varying means,.and said window timing varying means includes a controllable variable delay means in a signal path to said synchronizing means for adjustably delaying said first read signal;
• means for shifting said delay means;
• means for obtaining a maximum and minimum delay amount through said shifting means from said output from said window error detecting means;
• means for dividing the maximum and minimum delay amount into an arbitrary ratio;
• and
• means for setting said delay means at said divided delay amount.

A disk recording apparatus wherein a second read signal is produced from a first read signal read out from a disk shaped record medium, comprising:

• phase synchronizing means, into which said first read signal is input, for generating a clock pulse in synchronism with said first read signal;
• synchronizing means, into which said first read signal and said clock pulse produced from said phase synchronizing means are input, for producing said second read signal by employing a window which has been formed based upon said clock pulse;
• window error detecting means, into which the output from said synchronizing means is input, for judging whether an error of said second read signal has occurred or not;
• apparatus for reading out data from said window error detecting means which indicates whether an error of said second read signal has occurred or not and outputting control data which adjusts the timing of said window;
• window timing varying means for varying the relative timing of said window and said first read signal according to the data from said memory means;
• wherein said first read signal is inputted to said window timing varying means, and said window timing varying means includes a controllable variable delay means in a signal path to said synchronizing means for adjustably delaying said first read signal;
• wherein said delay means equipped with a tap includes an arrangement in which a CMOS inverter gate is alternately series-connected to a Bipolar-CMOS inverter gate.