Nonlinear analog to digital converter having first and second converters including serially connected circuit cells

An analog to digital converter, comprising:

• first conversion means having an input coupled to an analog input signal and a plurality of outputs for expressing, as a first digital value, an exponent of a floating point representation of the analog input signal, said first conversion means further having an analog signal output;
• and
• second conversion means having an input coupled to said analog signal output and a plurality of outputs for expressing, as a second digital value, a mantissa of the floating point representation of the analog input signal;
• wherein said first conversion means includes,
• (n) circuit cells, each of said (n) circuit cells having a first input node, a second input node, a first output node and a second output node, said (n) circuit cells being serially a second output node, said (n) circuit cells being serially coupled together in such a manner that said second output node of a first circuit cell is coupled to said first input node of a second circuit cell, each of said (n) circuit cells outputting one digital bit of a base 2 logarithmic expression, (n) being an order of the digital output bit wherein an (n)th circuit cell outputs an (n)th digital output bit;
• and
• wherein said first conversion means includes a first plurality of said circuit cells serially coupled together for performing logarithmic division of the analog input signal, said first converting means further having a second plurality of said circuit cells serially coupled together for implementing logarithmic multiplication of the analog input signal.

An electrical signal conversion circuit having an input for receiving an analog input signal, the circuit including means for converting the analog input signal to a multi-bit digital value that is a base 2 logarithmic representation of a magnitude of the analog input signal;

• wherein said converting means includes a plurality of circuit cells, each of said plurality of circuit cells having a first input node, a second input node, a first output node and a second output node, said plurality of circuit cells being serially coupled together in such a manner that said second output node of a first circuit cell is coupled to said first input node of a second circuit cell, and wherein the analog input signal is coupled to the first input node of the first circuit cell, each of said plurality of circuit cells outputting one bit of the multi-bit digital value, each of said circuit cells comprising:
• means for comparing an analog signal that is coupled to said first input node to a first reference signal that is coupled to said second input node, a magnitude of the first reference signal being a function of an order of a corresponding digital output bit, said comparing means having an output coupled to said first output node for providing thereto one bit of the multi-bit digital value, a state of the bit indicating whether a magnitude of the analog signal is greater than or less than the magnitude of the first reference signal;
• means for providing a first analog signal having a magnitude that is a function of the magnitude of the analog signal and a second reference signal;
• means for providing a second analog signal having a magnitude that is approximately equal to a magnitude of the analog signal that is coupled to the first input node;
• and
• switching means, coupled to the output of said comparing means and responsive to the state of the bit output thereby, for switchably coupling either the first analog signal or the second analog signal to the second output node.