Bare die carrier

A bare semiconductor integrated circuit die carrier for use in testing semiconductor integrated circuits, comprising:

• a substrate which includes an inner perimeter which defines an opening and which includes an outer perimeter region;
• a multiplicity of I/O pads disposed in the outer perimeter region of said substrate;
• an interconnect circuit which includes a composite of a multiplicity of individual electrical conductors which are formed on a polymer dielectric deposited on a top surface of the substrate and extending across the opening;
• a fence that is formed integrally with the polymer dielectric and that is sized to receive the die and that upstands from a portion of the polymer dielectric that spans the opening;
• a multiplicity of die contact pads disposed on the interconnect circuit within said fence;
• wherein said multiplicity of electrical conductors form a multiplicity of electrical paths between said I/O pads and said die contact pads;
• a support member which abuts against a bottom surface of said interconnect circuit;
• a top cap;
• a bottom cap;
• and
• means for securing said substrate and the die between said top cap and said bottom cap with said substrate and the die disposed therebetween.

A bare semiconductor integrated circuit die carrier for use in testing semiconductor integrated circuits, comprising:

• a substrate defining an opening and an outer perimeter;
• a multiplicity of I/O pads disposed about the outer perimeter of said substrate;
• an interconnect circuit which includes a composite of a multiplicity of individual electrical conductors which are formed on a polymer dielectric which overlays a top surface of the substrate and which extends across the opening so as to form a flexible membrane that spans the opening;
• a multiplicity of die contact pads disposed on the interconnect circuit;
• wherein said multiplicity of electrical conductors form a multiplicity of electrical paths between said I/O pads and the die contact pads;
• a fence that is formed integrally with the polymer dielectric and that upstands from the polymer dielectric and that is sized to receive the die;
• a support member which abuts against a bottom surface of said interconnect circuit;
• a top cap;
• a bottom cap;
• means for securing said substrate and the die and said support member between said top cap and said bottom cap;
• and
• force means for applying a force normal to said support member;
• whereby the normal force planarizes said die contact pads with respect to each other to improve their contact with the die.

A bare semiconductor integrated circuit die carrier for use in testing semiconductor integrated circuits, comprising:

• a substrate defining an opening and an outer perimeter;
• a multiplicity of I/O pads disposed about the outer perimeter of said substrate;
• an interconnect circuit which includes a composite of a multiplicity of individual electrical conductors which are formed on a polymer dielectric;
• wherein said interconnect circuit overlays a top surface of the substrate and extends across the opening;
• a multiplicity of die contact pads disposed on the interconnect circuit which form a multiplicity of electrical paths between said I/O pads and the die contact pads in the flexible membrane;
• a multiplicity of electrically conductive particles embedded on the die contact pads in contact with individual conductors;
• a polymer dielectric fence upstanding from the polymer dielectric and contoured so as to align the die such that respective pads of the die directly overlay respective electrically conductive particles that contact the individual conductors;
• a top cap;
• a bottom cap;
• a support member that abuts against a bottom surface of said interconnect circuit;
• force means for applying a sufficient amount of force to an interface of the die and said interconnect circuit such that individual particles penetrate any nonconductive material formed on the pads of the die;
• means for securing said substrate and the die between said top cap and said bottom cap.

A bare semiconductor integrated circuit die carrier for use in testing semiconductor integrated circuit, comprising:

• a substrate which includes an outer perimeter region and a compliant interior region which is thinner than the outer perimeter region;
• a multiplicity of I/O pads disposed in the outer perimeter region of said substrate;
• an interconnect circuit which includes a composite of a multiplicity of individual electrical conductors which are formed on a polymer dielectric deposited on a top surface of said substrate;
• a fence that is sized to receive the die and that upstands from a portion of the polymer dielectric that overlays the interior region;
• a multiplicity of die contact pads disposed on a portion of the interconnect circuit within said fence;
• wherein said multiplicity of electrical conductors form a multiplicity of electrical paths between said I/O pads and said die contact pads;
• a top cap;
• a bottom cap;
• means for securing said substrate and the die between said top cap and said bottom cap;
• and
• means for applying a force normal to said substrate;
• whereby the normal force pushes said substrate interior toward said semiconductor circuit so as to planarize said die contact pads with respect to each other to improve their connection with the semiconductor circuit.