Momentary test mode enabling circuit

A momentary test mode enabling circuit, comprising:

• a level detecting unit for detecting a level of an input signal being inputted to an input pin;
• a Schmitt trigger unit for stabilizing the level of a signal detected at the level detecting unit and outputting the stabilized signal as clock signals;
• and
• a toggle and latch unit for outputting a test enabling signal upon the control of the clock signals from the Schmitt trigger unit;
• wherein said level detecting unit includes:
• a first NMOS transistor having a drain connected to the input pin through a resistor and a gate connected to the ground;
• a second NMOS transistor having a drain connected to a source of said first MOS transistor and a gate and a source connected in common to the ground;
• a third NMOS transistor having a drain connected to a connection node between the drain of the second NMOS transistor and the source of the first NMOS transistor and a gate and a source connected in common to a level detection node;
• and
• a PMOS transistor having a drain connected to the level detection node, a source connected to a power supply terminal and a gate connected to the ground, and
• wherein said level detecting unit outputs a detection signal of a ground voltage level when the level of the input signal being inputted to the input pin is below the ground voltage level and a detection signal of a power source voltage level when the level of the input signal being inputted to the input pin is greater that the ground voltage level.