Low voltage detecting circuit
AssigneeKabushiki Kaisha Toshiba
InventorIsao Yamakawa
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AssigneeKabushiki Kaisha Toshiba
InventorIsao Yamakawa
Estimating the term…
Disclosed herein is a circuit for limiting the output current I.sub.O of a power MOSFET T.sub.1. A resistor R.sub.2 converts the current I.sub.O into a low voltage V.sub.0. The low voltage V.sub.O is detected by a low-voltage detecting circuit. When the low voltage V.sub.O is higher than a predetermined value V.sub.OL, the output current I.sub.O of the power MOSFET T.sub.1 is limited. The low-voltage detecting circuit comprises bipolar transistors Q.sub.1 to Q.sub.4. The base and collector of the transistor Q.sub.1 are connected to each other. The collector of the transistor Q.sub.2 is connected to the emitter of the transistor Q.sub.1. The base and emitter of the transistor Q.sub.3 are connected to the bases of the transistors Q.sub.1 and Q.sub.2, respectively. The base and collector of the transistor Q.sub.4 are connected to the emitters of the transistors Q.sub.1 and Q.sub.3, respectively. The low voltage V.sub.O is applied to the node between the emitters of the transistors Q.sub. 2 and Q.sub.4.
A current-limiting circuit comprising:
A circuit comprising:
Dependencies are inferred from the claim text.