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US 5,402,019 AGranted
Phase startable clock device
AssigneeTektronix, Inc.
InventorsWilliam S. Drummond, Arthur J. Metz, Walter D. Fields
Life of this patent
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Abstract
Apparatus for generating a phase startable clock signal, comprises an oscillator for providing a continuous sinusoidal input signal, a control signal source for providing a control input signal having a transition between a first state and a second state at a selected time during the signal epoch of the sinusoidal input signal, and a phase splitter, track and holds, multipliers and a summation device for operating on the sinusoidal input signal with the control input signal to produce a sinusoidal output signal commencing with a predetermined phase at a predetermined time relative to the transition.
Claims23
A method of generating a phase startable clock signal, comprising:
- (a) providing a continuous sinusoidal input signal,
- (b) providing a control input signal having a transition between a first state and a second state at a selected time during the signal epoch of the sinusoidal input signal, and
- (c) operating on the sinusoidal input signal with the logic control input signal to produce a sinusoidal output signal commencing with a predetermined phase at a predetermined time relative to said transition.
Apparatus for generating a phase startable clock signal, comprising:
- a first means for providing a continuous sinusoidal input signal,
- a second means for providing a control input signal having a transition between a first state and a second state at a selected time during the signal epoch of the sinusoidal input signal, and
- a third means for operating on the sinusoidal input signal with the control input signal to produce a sinusoidal output signal commencing with a predetermined phase at a predetermined time relative to said transition.
A phase startable clock apparatus comprising:
- a quadrature splitter means for receiving a sinusoidal input signal and providing first and second sinusoidal output signals in quadrature,
- a first delay means for receiving the quadrature splitter means' first sinusoidal output signal and producing a first delayed output signal identical to the quadrature splitter means' first sinusoidal output signal with a phase lag of .THETA.,
- a second delay means for receiving the quadrature splitter means' second sinusoidal output signal and producing a second delayed output signal identical to the quadrature splitter means' second sinusoidal output signal with a phase lag of .THETA.,
- a first sampling means having an analog input for receiving the quadrature splitter means' first sinusoidal output signal, an analog output for providing an analog output signal, and a control input for receiving a control signal having an enable state and a disable state such that when the control signal is in the disable state the first sampling means produces an analog output signal that is identical to the analog input signal, and when the control signal is in the enable state, the sampling means holds at its analog output the voltage that was present at its analog input at the time the control signal transitioned from the disable state to the enable state,
- a second sampling means having an analog input for receiving the quadrature splitter means' second sinusoidal output signal, an analog output for providing an analog output signal, and a control input for receiving the control signal such that when the control signal is in the disable state, the second sampling means produces an analog output signal that is identical to the analog input signal, and when the control signal is in the enable state the sampling means holds at its analog output the voltage that was present at its analog input at the time the control signal transitioned from the disable state to the enable state,
- first and second multiplier means for each receiving two analog input signals and providing an analog output signal that is the product of the two analog input signals, wherein the first multiplier means receives its two analog input signals from the second delay means and the first sampling means' analog output respectively, and the second multiplier means receives its two input signals from the first delay means and the second sampler means' analog output respectively, and
- a summation means for combining the analog output signals from the first and second multiplier means and producing an analog output signal.
4 more elements
A phase startable clock apparatus comprising:
- a phase splitter means for receiving a sinusoidal input signal and producing a first split sinusoidal signal, a second split sinusoidal signal having a 120.degree. phase difference with the first split sinusoidal signal, and a third split sinusoidal signal having a 240.degree. phase difference with the first split sinusoidal signal and a 120.degree. phase difference with the second split sinusoidal signal,
- a first sampling means having an analog input for receiving the first split sinusoidal signal, an analog output for providing an analog output signal (a'(t)), a control input for receiving a control signal having an enable state and a disable state such that when the control signal is in the disable state, the first sampling means produces an analog output signal that is identical to the analog input signal, and when the control signal is in the enable state, the sampling means holds at its analog output the voltage that was present at its analog input at the time the control signal transitioned from the disable state to the enable state,
- a second sampling means having an analog input for receiving the second split sinusoidal signal, an analog output for providing an analog output signal (b'(t)), and a control input for receiving the control signal such that when the control signal is in the disable state, the second sampling means produces an analog output signal that is identical to the analog input signal, and when the control signal is in the enable state, the sampling means holds at its analog output the voltage that was present at its analog input at the time the control signal transitioned from the disable state to the enable state,
- a third sampling means having an analog input for receiving the third split sinusoidal signal, an analog output for providing an analog output signal (c'(t)), a control input for receiving the control signal such that when the control signal is in the disable state, the third sampling means produces an analog output signal that is identical to the analog input signal, and when the control signal is in the enable state, the sampling means holds at its analog output the voltage that was present at its analog input at the time the control signal transitioned from the disable state to the enable state,
- a first multiplier means having a continuous input for receiving the third split sinusoidal signal, a differential input for receiving the difference between the first and second sampling means' analog output signals, and an analog output for providing a first product output signal, the first multiplier means being operative to multiply the continuous input signal with the differential input signal to produce the first product output signal,
- a second multiplier means having a continuous input for receiving the first split sinusoidal signal, a differential input for receiving the difference between the second and third sampling means' analog output signals, and an analog output for providing a second product output signal, the second multiplier being operative to multiply the continuous input signal with the differential input signal to produce the second product output signal,
- a third multiplier means having a continuous input for receiving the second split sinusoidal signal, a differential input for receiving the difference between the third and first sampling means' analog output signals, and an analog output for providing a third product output signal, the third multiplier being operative to multiply the continuous input signal with the differential input signal to produce the third product output signal, and
- a summation means for combining the first, second and third product output signals to produce an output signal.
5 more elements
A phase startable clock apparatus comprising:
- a quadrature splitter means for receiving a sinusoidal input signal and providing first and second sinusoidal output signals in quadrature,
- a first sampling means having an analog input for receiving the quadrature splitter means' first sinusoidal output signal, an analog output for providing an analog output signal, and a control input for receiving a control signal having an enable state and a disable state such that when the control signal is in the disable state, the first sampling means produces an analog output signal that is identical to the analog input signal, and when the control signal is in the enable state, the sampling means holds at its analog output the voltage that was present at its analog input at the time the control signal transitioned from the disable state to the enable state,
- a second sampling means having an analog input for receiving the quadrature splitter means' second sinusoidal output signal, an analog output for providing an analog output signal, and a control input for receiving the control signal such that when the control signal is in the disable state, the second sampling means produces an analog output signal that is identical to the analog input signal, and when the control signal is in the enable state, the sampling means holds at its analog output the voltage that was present at its analog input at the time the control signal transitioned from the disable state to the enable state,
- first and second multiplier means for each receiving two analog input signals and providing one analog output signal that is the product of the two analog input signals, wherein the first multiplier means receives its two analog input signals from the quadrature splitter's first sinusoidal output and the first sampling means' analog output respectively, and the second multiplier means receives its two analog input signals from the quadrature splitter's second analog output and the second sampling means' analog output respectively, and
- a summation means for combining the analog output signals from the first and second multiplier means and producing an analog output signal.
2 more elements
Dependencies are inferred from the claim text.