Integrated high-speed bipolar logic circuit
AssigneeTexas Instruments Incorporated
InventorShigeru Nakagawa
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AssigneeTexas Instruments Incorporated
InventorShigeru Nakagawa
Estimating the term…
To provide a type of logic circuit, characterized by the fact that the novel-configuration logic circuit can be easily manufactured in a bipolar process, having a high integration degree and allowing a high-speed operation. For standard longitudinal-type NPN transistor TR0, its emitter E0 is connected to bias terminal BIAS, base B0 is connected to voltage source+Vcc, and collector C0 is connected to base B1 of PNP transistor TR1. For lateral-type PNP transistor TR1, emitter E1 is connected to voltage source Vxx, base B1 is connected to both the collector Co of NPN transistor TR0 and input terminal IN, and collectors C1, C2, C3, . . . Cn are connected to output terminals OUT1, OUT2, PUT3, . . .OUTn, respectively. Schottky diodes SBD1, SBD2, SBD3, . . .SBDn are connected between base B1 and collectors C1, C2, C3, . . . Cn of NPN transistor TR1 with a cathode on the side of the base and with an anode on the side of the collector.
A logic circuit comprising:
Dependencies are inferred from the claim text.
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No related US applications are recorded in the indexed filing history.
Using semiconductor devices: using bipolar transistors
Modifications for accelerating switching: in bipolar transistor circuits
Pulse technique
Term ended 24 May 2013 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
This invention concerns a type of logic circuit. More specifically, this invention concerns a type of bipolar logic circuit made of bipolar transistors.
In the prior art, DTL (Diode Transistor Logic) and I.sup.2 L (Integrated Injection Logic) are the typical bipolar logic circuits with low voltage and low power consumption.
FIG. 5 shows an example of DTL. It is made of NPN transistor Trl, diodes D1, D2, and D3, bipolar resistors R1, R2, and R3, and NPN transistor Tr2. In this DTL basic circuit, when at least one of the input signals has voltage on level "L", NPN transistor Tr2 is OFF, and the "H" level output signal is obtained at its collector (output terminal). Only when all of the input signals are on the "H" level is NPN transistor Tr2 ON, and an "L" level output signal is obtained at the collector (output terminal). In this way, the DTL basic circuit acts as a NAND gate.
FIG. 1 is a circuit diagram illustrating the basic configuration of the logic circuit in an embodiment of this invention.
FIG. 2 is a cross-sectional view illustrating the configuration when the logic circuit in the embodiment is formed as a semiconductor IC.
FIG. 3 is an upper view illustrating the layout of the configuration when the logic circuit in the embodiment is formed as a semiconductor IC.
In the following, this invention will be explained in more detail with reference to embodiments illustrated by FIGS. 1-4.
FIG. 1 shows the basic configuration of the logic circuit in an embodiment in this invention. This logic circuit consists of one NPN transistor TR0, one multicollector PNP transistor TR1, and multiple Schottky diodes SBD1, SBD2, SBD3, . . . SBDn.
Emitter E0 of NPN transistor TR0 is connected to bias terminal BIAS. Base B0 is connected to voltage source Vcc and collector C0 is connected to base B1 of PNP transistor TR1. For PNP transistor TR1, emitter E1 is connected to voltage source Vcc, base B1 is connected to both collector CO of said NPN transistor TR0 and input terminal IN, and collectors C1, C2, C3, . . . Cn are connected to output terminals OUT1, OUT2, OUT3, . . . OUTn, respectively. Schottky diodes SBD1, SBD2, SBD3, . . . . SBDn are connected between base B1 and collectors C1, C2, C3, . . . Cn of NPN transistor TR1, with the cathode on the side of base and with the anode on the side of the collector.