Back to results
US 5,402,012 AGranted
Sequentially clocked domino-logic cells
AssigneeVLSI Technology, Inc.
InventorSteven D. Thomas
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeVLSI Technology, Inc.
InventorSteven D. Thomas
Estimating the term…
The present invention relates to an implementation of domino logic using a logic cell which is not limited to the use of positive logic functions, and which can be implemented using MOS technology. A significant feature of the present invention relates to use of a single clock cycle to generate separate clock phases for a first function (e.g., carry function of a full-adder logic cell) and a second function (e.g., sum function in the full-adder logic cell). The separate clock phase used to gate the second function corresponds to a delayed version of the clock phase used to gate the first function, wherein the clock delay corresponds to a delay through the first function. In one exemplary embodiment, the delay can be made equal to that of the first function by using circuitry identical to that of the first function to create the delay period.
Apparatus for logically combining digital logic values comprising:
A clock circuit for use in a domino logic cell implemented with negative logic, said clock circuit comprising:
An apparatus for implementing a logical function comprising:
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
No related US applications are recorded in the indexed filing history.
Adding; Subtracting: half or full adders, i.e. basic adder cells for one denomination
Synchronous circuits, i.e. using clock signals: using transistors of complementary type
Computing and data processing
Pulse technique
Term ended 19 Apr 2013 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
The present invention relates generally to digital signal processing, and more particularly to processing of digital signals using a logic cell suitable for a domino logic implementation.
2. State of the Art
The present invention can be further understood with reference to the following description and the appended drawings, wherein like elements are provided with the same reference numerals. In the drawings:
FIG. 1 shows an exemplary MOS implemented full-adder cell designed in accordance with an exemplary embodiment of the present invention;
FIG. 2 shows an exemplary carry function performing means for use with the FIG. 1 cell;
In exemplary embodiments of the present invention, the addition function of a full-adder will be used to illustrate the significant advantages which can be realized by the present invention. In accordance with an exemplary embodiment, the addition function is separated into two logical functions: a first function designated herein as a carry function, and a second function designated herein as a sum function. In accordance with exemplary embodiments of the present invention, two separately phased clocks ph1 and ph1d are generated from a single clock and used to separately clock the carry function and the sum function in any number of cascaded stages.
For example, FIG. 1 shows an apparatus for logically combining digital logic values, the apparatus being generally designated as a logic cell 100. Where the apparatus 100 is a logic cell for adding input signals, it includes a means for performing a first function, generally designated as a carry function performing means 200, and a means for performing a second function, generally designated as a sum function performing means 300.
The means for performing a carry function and the means for performing a sum function receive input signals via an input means 102. As illustrated in FIG. 1, three signal inputs labelled A, B and C are provided as inputs to the carry function performing means and the sum function performing means. The carry function performing means produces a carry output 104 labelled C'. The sum function performing means produces a sum output 106 labelled S'.