Pulse generator for generating a variable-width pulse having a small delay

A pulse generator for generating a variable width pulse, comprising:

• a first terminal connected to receive clock signals;
• a second terminal connected to receive a data signal indicating a number of clock signals corresponding to a desired pulse width;
• a third terminal connected to receive an enable signal;
• a down counter having a data terminal connected to said second terminal, an enable terminal connected to said third terminal and a clock terminal connected to said first terminal, said down counter counting down the number of clock signals indicated by said data signal, when said enable signal is received, in synchronism with said clock signals and generating output signals indicating a counted number;
• a flop-flop, having an enable terminal connected to said third terminal and a clock terminal connected to said first terminal, said flip-flop outputting a first state signal which indicates an initiation of the counting down by said down counter, said first state signal being used to generate a start of said variable width pulse;
• and
• a detection circuit connected to a receive said output signals from said down counter, said detection circuit detecting when said output signals indicate that the counted number is a particular number and producing a second state signal indicating an end of said variable width pulse.