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US 5,402,003 AGranted
Low dielectric constant interconnect for multichip modules
AssigneeTRW Inc.
InventorsGeorge W. McIver, Paula R. Hurt, John E. Dowsing, III
Life of this patent
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AssigneeTRW Inc.
InventorsGeorge W. McIver, Paula R. Hurt, John E. Dowsing, III
Estimating the term…
A substrate applicable to be used in a multichip module including a plurality of integrated circuits. The substrate includes a series of interrelated metal layers, ceramic layers and lattice structures formed by the ceramic layers. The metal layers provide ground planes, power planes and interconnects for the integrated circuit. The lattice structure consists of a series of ceramic regions separating the ceramic layers such that the majority of the lattice structure is air in order to reduce the effective dielectric constant of the substrate.
A substrate for supporting at least one integrated circuit, said substrate comprising:
A substrate applicable to support a plurality of integrated circuits associated with a multichip module, said substrate comprising:
A substrate used in association with a plurality of integrated circuit chips forming a multichip module, said substrate and associated integrated circuits being included in a single housing, said substrate comprising:
Dependencies are inferred from the claim text.
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High frequency adaptations: dielectric details, e.g. changing the dielectric material around a transmission line
Insulating or insulated package substrates; Interposers; Redistribution layers: for connecting multiple chips together
Characterised by their interconnections: shapes or dispositions of interconnections
Characterised by their insulating layers or insulating parts: shapes or dispositions thereof
Term ended 12 Nov 2013 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
This invention relates generally to a substrate having a reduced dielectric constant and, more particularly, to a substrate having a reduced dielectric constant for use in multichip modules in which the substrate includes a series of spaced apart ceramic layers defining lattice structures therebetween for trapping air.
2. Discussion of the Related Art
FIG. 1 is a cross sectional cut-away view of an MCM including a substrate according to a preferred embodiment of the present invention; and
FIG. 2 is a cut-away view of a section of the substrate of FIG. 1.
The following discussion of the preferred embodiments concerning a substrate for a multichip module is merely exemplary in nature and is in no way intended to limit the invention or its application or uses.
Turning to FIG. 1, a cross sectional cutaway view of a multichip module (MCM) 10 is shown. The MCM 10 includes several integrated circuit chips 12 configured on and interconnected throughout a substrate 14, according to a preferred embodiment of the present invention. The MCM 10, and associated integrated circuit chips 12 and the substrate 14, are configured within a hermetically sealed, ceramic housing 16. The MCM 10 is shown in a cutaway format to expose the different layers of the substrate 14.
As is apparent from viewing FIG. 1, the substrate 14 includes a series of stacked layers. In particular, a plurality of metal layers 18, solid ceramic layers 20 and lattice structure layers 22 are shown. The metal layers 18 are deposited and patterned on the ceramic layers 20 opposite to the lattice structure layers 22 so as to provide power and ground planes to the different circuits associated with the integrated circuit chips 12. The metal layers 18 are also patterned to provide interconnects between the integrated circuit chips 12. The ceramic layers 20 define the lattice structure layers 22. The solid ceramic layers 20 and the lattice structure layers 22 form dielectric insulative layers separating the metal layers 18.